From: Paul Kocialkowski <paulk@sys-base.io>
To: Parthiban Nallathambi <parthiban@linumiz.com>
Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Maxime Ripard <mripard@kernel.org>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Linus Walleij <linus.walleij@linaro.org>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
iommu@lists.linux.dev, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH 10/22] pinctrl: sunxi: add missed lvds pins for a100/a133
Date: Wed, 25 Jun 2025 10:46:52 +0200 [thread overview]
Message-ID: <aFu3fAMa8KPwjPbX@shepard> (raw)
In-Reply-To: <20241227-a133-display-support-v1-10-13b52f71fb14@linumiz.com>
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Hi and thanks for your work!
On Fri 27 Dec 24, 16:37, Parthiban Nallathambi wrote:
> lvds, lcd, dsi all shares the same GPIO D bank and lvds0
> data 3 lines and lvds1 pins are missed, add them.
Would it also make sense to submit device-tree pin definitions here?
Thanks!
Paul
> Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
> ---
> drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> index df90c75fb3c5..b97de80ae2f3 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> @@ -256,72 +256,84 @@ static const struct sunxi_desc_pin a100_pins[] = {
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
> + SUNXI_FUNCTION(0x3, "lvds0"), /* D3P */
> SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
> + SUNXI_FUNCTION(0x3, "lvds0"), /* D3N */
> SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D0P */
> SUNXI_FUNCTION(0x4, "spi1"), /* CS */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D0N */
> SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D1P */
> SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D1N */
> SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D2P */
> SUNXI_FUNCTION(0x4, "uart3"), /* TX */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D2N */
> SUNXI_FUNCTION(0x4, "uart3"), /* RX */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* CKP */
> SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* CKN */
> SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D3P */
> SUNXI_FUNCTION(0x4, "uart4"), /* TX */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
> + SUNXI_FUNCTION(0x3, "lvds1"), /* D3N */
> SUNXI_FUNCTION(0x4, "uart4"), /* RX */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
>
> --
> 2.39.5
>
--
Paul Kocialkowski,
Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/
Expert in multimedia, graphics and embedded hardware support with Linux.
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next prev parent reply other threads:[~2025-06-25 8:47 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-27 11:07 [PATCH 00/22] Add support for A100/A133 display Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 01/22] dt-bindings: iommu: sun50i: remove resets from required property Parthiban Nallathambi
2025-08-07 15:27 ` Paul Kocialkowski
2024-12-27 11:07 ` [PATCH 02/22] dt-bindings: display: sunxi: Add a100/a133 display engine compatibles Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 03/22] dt-bindings: clock: sun8i de2 clock: Add PLL com clock Parthiban Nallathambi
2024-12-27 13:16 ` Rob Herring (Arm)
2024-12-27 11:07 ` [PATCH 04/22] dt-bindings: clock: sun8i de2 clock: Add a100/a133 compatible Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 05/22] dt-bindings: display: sun4i: add phy property Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 06/22] dt-bindings: display: sun4i: add a100/a133 tcon lcd Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 07/22] dt-bindings: vendor-prefixes: Shenzhen Baijie Technology Parthiban Nallathambi
2025-08-07 15:24 ` Paul Kocialkowski
2024-12-27 11:07 ` [PATCH 08/22] dt-bindings: arm: sunxi: document Szbaijie A133 helper board Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 09/22] iommu: sun50i: make reset control optional Parthiban Nallathambi
2025-01-06 11:24 ` Joerg Roedel
2025-08-07 15:29 ` Paul Kocialkowski
2024-12-27 11:07 ` [PATCH 10/22] pinctrl: sunxi: add missed lvds pins for a100/a133 Parthiban Nallathambi
2025-01-13 14:30 ` Linus Walleij
2025-01-14 15:46 ` Andre Przywara
2025-06-25 8:46 ` Paul Kocialkowski [this message]
2025-06-25 9:36 ` Parthiban
2025-06-25 10:11 ` Paul Kocialkowski
2025-06-25 10:46 ` Parthiban
2024-12-27 11:07 ` [PATCH 11/22] drm/sun4i: Add support for a100/a133 display engine Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 12/22] drm/sun4i: Add support for a100/a133 mixer Parthiban Nallathambi
2024-12-27 11:08 ` [PATCH 13/22] drm/sun4i: make tcon top tv0 optional Parthiban Nallathambi
2024-12-27 11:08 ` [PATCH 14/22] drm/sun4i: add a100/a133 tcon top quirks Parthiban Nallathambi
2024-12-27 11:08 ` [PATCH 15/22] clk: sunxi-ng: sun8i-de2: add pll-com clock support Parthiban Nallathambi
2024-12-27 11:08 ` [PATCH 16/22] clk: sunxi-ng: sun8i-de2: Add support for a100/a133 Parthiban Nallathambi
[not found] ` <20241227-a133-display-support-v1-17-13b52f71fb14@linumiz.com>
2025-06-25 8:41 ` [PATCH 17/22] phy: allwinner: phy-sun6i-mipi-dphy: add LVDS support Paul Kocialkowski
2025-06-25 9:38 ` Parthiban
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