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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Z0fcf88ABTsqcmaWqPJqmEVA+UNCkosdFyoDPzBwx/0KtEc2fDsSo/xtb3oO?= =?us-ascii?Q?9zilOkejUV4Jayc51flgx+FFargduLhLtAvAq+e3I49WWrT2MuFOFDubz3GE?= =?us-ascii?Q?Z3h+asJq0FL8CJpXV+dT5EYTyabGHsnDpO6cT0Mo46iA3bnVwW0C/J2qZ6vN?= =?us-ascii?Q?lS1JAJEEByZoAGb34j6hvpiDfLkKVqYcjqoN8sJ0+rJBntorbXGj51K04ZhB?= =?us-ascii?Q?dJa2MO5oGu7HZ+DoVzeaM/TV35zWB8XVSh+mPs2+YaiysZh9b4lUX2/oYsTs?= =?us-ascii?Q?LSul0zjYKtBrI6Yo2xXfr0u3DkM34+FBhkaZMLO2mlfJMSuiybLbrSpIlebs?= =?us-ascii?Q?nTuTPRnPXqLubMjA7QFUf7vyI95ufRaAsuCCdB3G2SRmOBWBdRvVCk0uatL3?= =?us-ascii?Q?ePZW5Cb0qsoEFxTDjzCF20EGNtmV7GSeO2UIES30uQnRyHH2aeFo74Lft5yZ?= =?us-ascii?Q?YEQaO9liFDo/weiaZc/kQumvF/9nZ8o5DjDHDkMJUD9cbo6ujM+9WLwgIwsE?= =?us-ascii?Q?LGX2lylgVBRxoqa6p/VpgPxvkflv/gwsv9dvWZz7/rIQSq5/MCDptbiGWxVc?= =?us-ascii?Q?D1wrccQwF2k6wY75VgjREDF7xtV0+HL0gaZ4wLfIh8lDo7PB5fyzt0zf362s?= =?us-ascii?Q?v6+/vObqt12DmlvGcLgwQnTmKhNEXW4p70doW2IeYci+/tzl+GPoQMVrlYYw?= =?us-ascii?Q?5hQBLRkyxGUtgPjvwRjr0uQGNenuT6xBb9SBV5/0vAAlrM5JBn/cp5hHI4An?= =?us-ascii?Q?lugLj6vTF9tnw75BaDfkXkhww7b19435Lcd5XFigW9sKgc/dyKtuRP07IbeF?= =?us-ascii?Q?eHPmqs059J54wvvTKDhCB9TTXgOSHC0d6eZrB4Sx2i/zTFCvmyarO2tibPyG?= =?us-ascii?Q?diI6eup8+Cl9gz3D6oGuk682oWClu3oUxc04a9pZyOCotYyRQ7LwLI4NtWX0?= =?us-ascii?Q?iCBSnZrsWJeYlqnwtkiLiTPFvYs7cr3+2pkrFI11VaS2KUGSGi6FTkJlDDxO?= =?us-ascii?Q?fKHcygFAlFgVr4lK8C1ZIC3eM8ZvAV/5lG/R6YXGSFCIWlXMx+xxKwkdmUiE?= =?us-ascii?Q?5EFz9nSXGE24A7bk8Ofhwbxd222yUKmK69Ytp9vwWxSnUUamAYLRL/8WNl6E?= =?us-ascii?Q?zzrRCA3evgiXMwrAg1TEoZ4PTgaYnP9Rx4zljNz5vGlhKuBdHmNztSQKdTCT?= =?us-ascii?Q?093mk2TVrn0Z++HYOosr2fN3xxNNOhlJWycZq0le4Y+mbNUWj/m/FAFjk8i+?= =?us-ascii?Q?CPYaHXwbPVuJtaEx6/SVa3wXNiQmG8jgRMqRvlBvsmXmvjBRJquNgyKXtJYA?= =?us-ascii?Q?v+Wl6C0w1UJXjeBgW/+rZLnp+g1T1YHqlR7KiH8kxhM//kmmqZ49VaIHDaWq?= =?us-ascii?Q?6HIqYYnNkMTd5CnQcK7rdzrAS+msNZIQSSioK1brafJ10Ui0Ke22PIey9S1r?= =?us-ascii?Q?fffV3eHABd//zTozS+6aka6C5rp270Z7HCGbRb380nmLhwiWTifemxAjAlCm?= =?us-ascii?Q?UNXTfGFqCUz2ypw7LhniUJkgsYhBxfUvfpskxuXWu5eIKoMUWgcq3nJO8UDG?= =?us-ascii?Q?+lsNo7J3VwMyJ5lX7AuvenhnYkEnok5oKX5Ia3pM?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ac19d53c-6340-4791-6ae3-08ddbfc95896 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 15:49:25.5155 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nD95uKYRmBH+vYyvOChtUEWVUrFDg2UZfv9alcSNvlVm2uTXEM1sbaDv78AIpA858MoTwpGnf0bZKjgaTEI+gg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7223 On Thu, Jul 10, 2025 at 05:20:24PM +0300, Andrei Stefanescu wrote: > Add the dt-bindings for the NXP SIUL2 module which is a multi > function device. It can export information about the SoC, configure > the pinmux&pinconf for pins and it is also a GPIO controller with > interrupt capability. wrap at 75 chars. > > Signed-off-by: Andrei Stefanescu > --- > .../bindings/mfd/nxp,s32g2-siul2.yaml | 163 ++++++++++++++++++ > 1 file changed, 163 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yaml > > diff --git a/Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yaml b/Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yaml > new file mode 100644 > index 000000000000..8ae185b4bc78 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yaml > @@ -0,0 +1,163 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright 2024 NXP > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mfd/nxp,s32g2-siul2.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP S32 System Integration Unit Lite2 (SIUL2) > + > +maintainers: > + - Andrei Stefanescu > + > +description: | > + SIUL2 is a hardware block which implements pinmuxing, > + pinconf, GPIOs (some with interrupt capability) and > + registers which contain information about the SoC. > + There are generally two SIUL2 modules whose functionality > + is grouped together. For example interrupt configuration > + registers are part of SIUL2_1 even though interrupts are > + also available for SIUL2_0 pins. > + > + The following register types are exported by SIUL2: > + - MIDR (MCU ID Register) - information related to the SoC > + - interrupt configuration registers > + - MSCR (Multiplexed Signal Configuration Register) - pinmuxing and pinconf > + - IMCR (Input Multiplexed Signal Configuration Register)- pinmuxing > + - PGPDO (Parallel GPIO Pad Data Out Register) - GPIO output value > + - PGPDI (Parallel GPIO Pad Data In Register) - GPIO input value > + > + Most registers are 32bit wide with the exception of PGPDO/PGPDI which are > + 16bit wide. > + > +properties: > + compatible: > + oneOf: > + - const: nxp,s32g2-siul2 > + - items: > + - enum: > + - nxp,s32g3-siul2 > + - const: nxp,s32g2-siul2 > + > + reg: > + minItems: 2 > + > + reg-names: > + items: > + - const: siul20 > + - const: siul21 > + > + gpio-controller: true > + > + "#gpio-cells": > + const: 2 > + > + gpio-ranges: > + maxItems: 2 > + > + interrupts: > + maxItems: 1 > + > + interrupt-controller: true > + > + "#interrupt-cells": > + const: 2 > + > + nvmem-layout: > + $ref: /schemas/nvmem/layouts/nvmem-layout.yaml# > + description: > + This container may reference an NVMEM layout parser. > + > +patternProperties: > + "-hog(-[0-9]+)?$": > + required: > + - gpio-hog > + > + "-pins$": > + type: object > + additionalProperties: false > + > + patternProperties: > + "-grp[0-9]$": > + type: object > + allOf: > + - $ref: /schemas/pinctrl/pinmux-node.yaml# > + - $ref: /schemas/pinctrl/pincfg-node.yaml# > + description: > + Pinctrl node's client devices specify pin muxes using subnodes, > + which in turn use the standard properties below. > + > + properties: > + bias-disable: true > + bias-high-impedance: true > + bias-pull-up: true > + bias-pull-down: true > + drive-open-drain: true > + input-enable: true > + output-enable: true I remember you needn't mark these as true, default it should be true if use "unevaluatedProperties: false". Can you check if pass dt_binding_check if remove these property? > + > + pinmux: > + description: | > + An integer array for representing pinmux configurations of > + a device. Each integer consists of a PIN_ID and a 4-bit > + selected signal source(SSS) as IOMUX setting, which is > + calculated as: pinmux = (PIN_ID << 4 | SSS) Do you have include file to define it? otherwise hex value is not easy understand. Frank > + > + slew-rate: > + description: Supported slew rate based on Fmax values (MHz) > + enum: [83, 133, 150, 166, 208] > + required: > + - pinmux > + > + unevaluatedProperties: false > + > +required: > + - compatible > + - reg > + - reg-names > + - gpio-controller > + - "#gpio-cells" > + - gpio-ranges > + - interrupts > + - interrupt-controller > + - "#interrupt-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + pinctrl@4009c000 { > + compatible = "nxp,s32g2-siul2"; > + reg = <0x4009c000 0x179c>, > + <0x44010000 0x17b0>; > + reg-names = "siul20", "siul21"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&siul2 0 0 102>, <&siul2 112 112 79>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = ; > + > + jtag-pins { > + jtag-grp0 { > + pinmux = <0x0>; > + input-enable; > + bias-pull-up; > + slew-rate = <166>; > + }; > + }; > + > + nvmem-layout { > + compatible = "fixed-layout"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + soc-major@0 { > + reg = <0 0x4>; > + }; > + }; > + }; > +... > -- > 2.45.2 >