From: Paul Kocialkowski <paulk@sys-base.io>
To: Maxime Ripard <mripard@kernel.org>
Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-gpio@vger.kernel.org, Yong Deng <yong.deng@magewell.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Linus Walleij <linus.walleij@linaro.org>,
Icenowy Zheng <icenowy@aosc.xyz>,
Andre Przywara <andre.przywara@arm.com>
Subject: Re: [PATCH 5/5] drm/sun4i: Run the mixer clock at 297 MHz on V3s
Date: Wed, 2 Jul 2025 14:15:46 +0200 [thread overview]
Message-ID: <aGUi8ot1-0WaReyp@collins> (raw)
In-Reply-To: <20250702-psychedelic-stalwart-jerboa-a626eb@houat>
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Hi Maxime,
Le Wed 02 Jul 25, 13:36, Maxime Ripard a écrit :
> On Tue, Jul 01, 2025 at 10:11:24PM +0200, Paul Kocialkowski wrote:
> > The DE mixer clock is currently set to run at 150 MHz, while the
> > Allwinner BSP configures it at 300 MHz and other platforms typically
> > run at 297 MHz.
> >
> > 150 MHz appears to be enough given the restricted graphics capabilities
> > of the SoC (with a work area of only 1024x1024). However it typically
> > causes the DE clock to be parented to the periph0 pll instead of the
> > video PLL.
> >
> > While this should generally not be a concern, it appears (based on
> > experimentation) that both the DE and TCON clocks need to be parented
> > to the same PLL for these units to work. While we cannot represent this
> > constraint in the clock driver, it appears that the TCON clock will
> > often get parented to the video pll (typically running at 297 MHz for
> > the CSI units needs), for instance when driving displays with a 33 MHz
> > pixel clock (33 being a natural divider of 297).
> >
> > Running the DE clock at 297 MHz will typically result in parenting to
> > the video pll instead of the periph0 pll, thus making the display
> > output functional.
> >
> > This is all a bit fragile but it solves the issue with displays running
> > at 33 Mhz and brings V3s to use the same frequency as other platforms,
> > making support more unified.
>
> It's beyond fragile, and doesn't have anything to do with the DRM driver.
>
> You should set up the clock tree properly in the clock driver, and then
> add NO_REPARENT to the DE clock to make sure it stays that way.
Thanks for the suggestion! I wasn't aware there was a flag to avoid
reparenting, sounds like the most reasonable way to solve this issue then.
I'll send another iteration reworking the clock tree then.
> And then, you can change the clock rate if you want to, but at least you
> don't set a rate and hope that the side effects work your way, and won't
> happen again.
We might as well still change it. To be honest I don't really see why it was
set to 150 MHz in the first place.
Cheers,
Paul
--
Paul Kocialkowski,
Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/
Expert in multimedia, graphics and embedded hardware support with Linux.
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next prev parent reply other threads:[~2025-07-02 12:16 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-01 20:11 [PATCH 0/5] sunxi: Various minor V3s clock/pinctrl fixes Paul Kocialkowski
2025-07-01 20:11 ` [PATCH 1/5] pinctrl: sunxi: v3s: Fix wrong comment about UART2 pinmux Paul Kocialkowski
2025-07-02 3:04 ` Icenowy Zheng
2025-07-02 7:21 ` Chen-Yu Tsai
2025-07-04 8:01 ` Linus Walleij
2025-07-01 20:11 ` [PATCH 2/5] clk: sunxi-ng: v3s: Fix CSI SCLK clock name Paul Kocialkowski
2025-07-02 3:08 ` Icenowy Zheng
2025-07-01 20:11 ` [PATCH 3/5] clk: sunxi-ng: v3s: Fix CSI1 MCLK " Paul Kocialkowski
2025-07-02 3:10 ` Icenowy Zheng
2025-07-01 20:11 ` [PATCH 4/5] clk: sunxi-ng: v3s: Fix TCON clock parents Paul Kocialkowski
2025-07-01 20:11 ` [PATCH 5/5] drm/sun4i: Run the mixer clock at 297 MHz on V3s Paul Kocialkowski
2025-07-02 2:52 ` Icenowy Zheng
2025-07-02 11:36 ` Maxime Ripard
2025-07-02 12:15 ` Paul Kocialkowski [this message]
2025-07-03 15:37 ` (subset) [PATCH 0/5] sunxi: Various minor V3s clock/pinctrl fixes Chen-Yu Tsai
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