From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E80BF70823; Thu, 3 Jul 2025 16:04:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751558673; cv=none; b=eTT8F8KdIHhKFj1Ijh8ID23snptvyRFTu12Q/oieXqS1WFwY0NRD5C5cp3IHn/EAN3yz3ZyW12g1JfkcuQrgQPkcY8Uxiz0xlpBuo5z9A3fJCnNwg9cDxgkMG0K4wjFVfEMvytx+X6I08Jo+2JvxE9/cQyAtRFg4bbA7vRm7GnE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751558673; c=relaxed/simple; bh=58aM0K/86rOEBlpZHaNUBM3QI7pc8TJva4aXr53+6X0=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Tr0TLXNAHcf4mXTqKb8zs+OaKU/g13uoMPG7Uwyna2701JdrTSy7920NxwVilzuC07E7z7LcJtXqz0h+nO/xXuHuz5s87nUkNERvNdLpeT/JiHHh+FyF2+Hf1qWZovV8AJ+UcaI1g/WsVh4vTh+sEM96XfoJeln16XteGPAK8Is= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 17A1BC4CEEE; Thu, 3 Jul 2025 16:04:28 +0000 (UTC) Date: Thu, 3 Jul 2025 17:04:26 +0100 From: Catalin Marinas To: Lorenzo Pieralisi Cc: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Arnd Bergmann , Sascha Bischoff , Jonathan Cameron , Timothy Hayes , Bjorn Helgaas , "Liam R. Howlett" , Peter Maydell , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v7 18/31] arm64: smp: Support non-SGIs for IPIs Message-ID: References: <20250703-gicv5-host-v7-0-12e71f1b3528@kernel.org> <20250703-gicv5-host-v7-18-12e71f1b3528@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250703-gicv5-host-v7-18-12e71f1b3528@kernel.org> On Thu, Jul 03, 2025 at 12:25:08PM +0200, Lorenzo Pieralisi wrote: > From: Marc Zyngier > > The arm64 arch has relied so far on GIC architectural software > generated interrupt (SGIs) to handle IPIs. Those are per-cpu > software generated interrupts. > > arm64 architecture code that allocates the IPIs virtual IRQs and > IRQ descriptors was written accordingly. > > On GICv5 systems, IPIs are implemented using LPIs that are not > per-cpu interrupts - they are just normal routable IRQs. > > Add arch code to set-up IPIs on systems where they are handled > using normal routable IRQs. > > For those systems, force the IRQ affinity (and make it immutable) > to the cpu a given IRQ was assigned to. > > Signed-off-by: Marc Zyngier > [timothy.hayes@arm.com: fixed ipi/irq conversion, irq flags] > Signed-off-by: Timothy Hayes > [lpieralisi: changed affinity set-up, log] > Signed-off-by: Lorenzo Pieralisi > Cc: Will Deacon > Cc: Catalin Marinas Acked-by: Catalin Marinas