Re: [PATCH v2 1/2] phy: dw-dphy-rx: Add Synopsys DesignWare D-PHY RX

[Frank Li <Frank.li@nxp.com>]

On Thu, Jul 10, 2025 at 05:12:57AM +0000, Poduval, Karthik wrote:
> On Thu, 2025-07-10 at 00:08 -0400, Frank Li wrote:
> > CAUTION: This email originated from outside of the organization. Do
> > not click links or open attachments unless you can confirm the sender
> > and know the content is safe.
> >
> >
> >
...
> > > +
> > > +     dphy->dt_data =
> > > +             (struct dt_data_dw_dphy
> > > *)of_device_get_match_data(&pdev->dev);
> > > +     dev_set_drvdata(&pdev->dev, dphy);
> > > +     dphy->dev = &pdev->dev;
> > > +
> > > +     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > +     dphy->iomem_cfg1 = devm_ioremap_resource(&pdev->dev, res);
> > > +     if (IS_ERR(dphy->iomem_cfg1))
> > > +             return PTR_ERR(dphy->iomem_cfg1);
> >
> > cfg1 is part of DW MIPI-CSI2 MMIO space. how to cooperate with dw
> > MIPI-CSI2
> > controller.
> This is essentially why we created two MMIO spaces as CSI2 and D-PHY
> are intermixed in the MMIO space and regmap driver detects the
> conflict.

Because there are not CSI2 part code, It is not clear how to avoid this
problem by use cfg1 and cfg2.

CSI2 register look like
 version
 n_lan
 ...
 phy_tst_ctrl1
 phy_tst_ctrl2
 ...
 other register like irqs

Frank

> >
> > Please CC me for next version. I am working on DW MIPI-CSI2 work.
> >
> > https://lore.kernel.org/imx/20250701-95_cam-v1-5-c5172bab387b@nxp.com/
> >
> > Frank
> Sure, Frank, perhaps loop in Miguel as he might be able to know about
> all the variants out there for this IP.

...
> > > +MODULE_LICENSE("GPL");
> > > --
> > > 2.43.0
> > >
>