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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8e14ce6sm18964814f8f.68.2025.07.16.13.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jul 2025 13:12:54 -0700 (PDT) Date: Wed, 16 Jul 2025 22:12:53 +0200 From: Daniel Lezcano To: Nicolas Frattaroli Cc: Alexey Charkov , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jonas Karlman , Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Ye Zhang Subject: Re: [PATCH v6 0/7] RK3576 thermal sensor support, including OTP trim adjustments Message-ID: References: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> On Tue, Jun 10, 2025 at 02:32:36PM +0200, Nicolas Frattaroli wrote: > This series adds support for the RK3576's thermal sensor. > > The sensor has six channels, providing measurements for the package > temperature, the temperature of the big cores, the temperature of the > little cores, and the GPU, NPU and DDR controller. > > In addition to adding support for the sensor itself, the series also > adds support for reading thermal trim values out of the device tree. > Most of this functionality is not specific to this SoC, but needed to be > implemented to make the sensors a little more accurate in order to > investigate whether the TRM swapped GPU and DDR or downstream swapped > GPU and DDR in terms of channel IDs, as downstream disagrees with what's > in the TRM, and the difference is so small and hard to pin down with > testing that the constant offset between the two sensors was a little > annoying for me to deal with. > > I ended up going with the channel assignment the TRM lists, as I see the > DDR sensor get a larger deviation from baseline temperatures during memory > stress tests (stress-ng --memrate 8 --memrate-flush) than what the TRM > claims is the GPU sensor but downstream claims is the DDR sensor. Input > from Rockchip engineers on whether the TRM is right or wrong welcome. > > The trim functionality is only used by RK3576 at the moment. Code to > handle other SoCs can rely on the shared otp reading and perhaps even > the IP revision specific function, but may need its own IP revision > specific functions added as well. Absent trim functionality in other > SoCs should not interfere with the modified common code paths. > > Patch 1 is a cleanup patch for the rockchip thermal driver, where a > function was confusingly named. > > Patch 2 adds the RK3576 compatible to the bindings. > > Patch 3 adds support for this SoC's thermal chip to the driver. It is a > port of the downstream commit adding support for this. > > Patch 4 adds some documentation for imminent additional functionality to > the binding, namely the trim value stuff. > > Patch 5 adds support for reading these OTP values in the > rockchip_thermal driver, and makes use of them. The code is mostly new > upstream code written by me, using downstream code as reference. Replaced previously applied version V5 with this V6 patches 1-5 Thanks -- Daniel -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog