From: Will Deacon <will@kernel.org>
To: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Cc: joro@8bytes.org, robin.murphy@arm.com, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de,
nicolas.dufresne@collabora.com, jgg@ziepe.ca,
iommu@lists.linux.dev, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, kernel@collabora.com
Subject: Re: [PATCH v6 3/5] iommu: Add verisilicon IOMMU driver
Date: Fri, 18 Jul 2025 12:45:03 +0100 [thread overview]
Message-ID: <aHozv0NG1OBlAH6c@willie-the-truck> (raw)
In-Reply-To: <baa1fcde-f167-4a1b-afca-0a2957a688cc@collabora.com>
On Mon, Jul 14, 2025 at 04:56:53PM +0200, Benjamin Gaignard wrote:
> Le 14/07/2025 à 14:08, Will Deacon a écrit :
> > On Thu, Jul 10, 2025 at 10:24:44AM +0200, Benjamin Gaignard wrote:
> > > +/* vsi iommu regs address */
> > > +#define VSI_MMU_CONFIG1_BASE 0x1ac
> > > +#define VSI_MMU_AHB_EXCEPTION_BASE 0x380
> > > +#define VSI_MMU_AHB_CONTROL_BASE 0x388
> > > +#define VSI_MMU_AHB_TLB_ARRAY_BASE_L_BASE 0x38C
> > > +
> > > +/* MMU register offsets */
> > > +#define VSI_MMU_FLUSH_BASE 0x184
> > > +#define VSI_MMU_BIT_FLUSH BIT(4)
> > > +
> > > +#define VSI_MMU_PAGE_FAULT_ADDR 0x380
> > > +#define VSI_MMU_STATUS_BASE 0x384 /* IRQ status */
> > > +
> > > +#define VSI_MMU_BIT_ENABLE BIT(0)
> > > +
> > > +#define VSI_MMU_OUT_OF_BOUND BIT(28)
> > > +/* Irq mask */
> > > +#define VSI_MMU_IRQ_MASK 0x7
> > > +
> > > +#define VSI_DTE_PT_ADDRESS_MASK 0xffffffc0
> > > +#define VSI_DTE_PT_VALID BIT(0)
> > > +
> > > +#define VSI_PAGE_DESC_LO_MASK 0xfffff000
> > > +#define VSI_PAGE_DESC_HI_MASK GENMASK_ULL(39, 32)
> > > +#define VSI_PAGE_DESC_HI_SHIFT (32 - 4)
> > How does this page-table format relate to the one supported already by
> > rockchip-iommu.c? From a quick glance, I suspect this is a derivative
> > and so ideally we'd be able to have a common implementation of the
> > page-table code which can be used by both of the drivers.
> >
> > Similarly:
>
> No they comes from different IP providers, this one is from Verisilicon.
> I agree they looks very similar and my first attempt was to add it into
> rockchip-iommu code but when doing it I realize that registers addresses
> where all different so I had to code all the functions twice.
Understood, and I'm not suggesting to merge the drivers or try to
consolidate the register layouts. What I _am_ saying is that the
in-memory page-table format should be factored out in a way that can
be reused by the two drivers and also that some of the logic (as highlighted
by vsi_iommu_domain_free()) is practically identical between the drivers
and should also be shared.
Will
next prev parent reply other threads:[~2025-07-18 11:45 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-10 8:24 [PATCH v6 0/5] Add support for Verisilicon IOMMU used by media codec blocks Benjamin Gaignard
2025-07-10 8:24 ` [PATCH v6 1/5] dt-bindings: vendor-prefixes: Add Verisilicon Benjamin Gaignard
2025-07-10 8:24 ` [PATCH v6 2/5] dt-bindings: iommu: verisilicon: Add binding for VSI IOMMU Benjamin Gaignard
2025-07-10 8:24 ` [PATCH v6 3/5] iommu: Add verisilicon IOMMU driver Benjamin Gaignard
2025-07-14 12:08 ` Will Deacon
2025-07-14 14:56 ` Benjamin Gaignard
2025-07-18 11:45 ` Will Deacon [this message]
2025-07-18 12:56 ` Robin Murphy
2025-07-18 13:26 ` Jason Gunthorpe
2025-07-18 13:47 ` Will Deacon
2025-07-18 14:14 ` Jason Gunthorpe
2025-07-21 11:14 ` Benjamin Gaignard
2025-07-21 17:00 ` Will Deacon
2025-07-10 8:24 ` [PATCH v6 4/5] arm64: dts: rockchip: Add verisilicon IOMMU node on RK3588 Benjamin Gaignard
2025-07-10 8:24 ` [PATCH v6 5/5] arm64: defconfig: enable Verisilicon IOMMU Benjamin Gaignard
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