[PATCH v2 5/9] watchdog: rzv2h_wdt: Add support for configurable count clock source

Prabhakar
2025-07-29T15:59:28Z

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add support for selecting the count clock source used by the watchdog
timer. The RZ/V2H(P) SoC uses the LOCO as the count source, whereas on
RZ/T2H and RZ/N2H SoCs, the count source is the peripheral clock (PCLKL).

Introduce a `count_source` field in the SoC-specific data structure and
refactor the clock rate selection logic accordingly. This prepares the
driver for supporting the RZ/T2H and RZ/N2H SoCs, which differ in their
watchdog clocking architecture from RZ/V2H(P).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- No changes.
---
drivers/watchdog/rzv2h_wdt.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c
index baf9d64510b9..cb584ac5860f 100644
--- a/drivers/watchdog/rzv2h_wdt.c
+++ b/drivers/watchdog/rzv2h_wdt.c
@@ -44,10 +44,16 @@ module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

+enum rzv2h_wdt_count_source {
+ COUNT_SOURCE_LOCO,
+ COUNT_SOURCE_PCLK,
+};
+
struct rzv2h_of_data {
u8 cks_min;
u8 cks_max;
u16 cks_div;
+ enum rzv2h_wdt_count_source count_source;
};

struct rzv2h_wdt_priv {
@@ -213,6 +219,7 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct rzv2h_wdt_priv *priv;
+ struct clk *count_clk;
int ret;

priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -238,8 +245,18 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(priv->rstc),
"failed to get cpg reset");

+ switch (priv->of_data->count_source) {
+ case COUNT_SOURCE_LOCO:
+ count_clk = priv->oscclk;
+ break;
+ case COUNT_SOURCE_PCLK:
+ count_clk = priv->pclk;
+ break;
+ default:
+ return dev_err_probe(dev, -EINVAL, "Invalid count source\n");
+ }
priv->wdev.max_hw_heartbeat_ms = (MILLI * MAX_TIMEOUT_CYCLES * priv->of_data->cks_div) /
- clk_get_rate(priv->oscclk);
+ clk_get_rate(count_clk);
dev_dbg(dev, "max hw timeout of %dms\n", priv->wdev.max_hw_heartbeat_ms);

ret = devm_pm_runtime_enable(dev);
@@ -266,6 +283,7 @@ static const struct rzv2h_of_data rzv2h_wdt_of_data = {
.cks_min = WDTCR_CKS_CLK_1,
.cks_max = WDTCR_CKS_CLK_256,
.cks_div = 256,
+ .count_source = COUNT_SOURCE_LOCO,
};

static const struct of_device_id rzv2h_wdt_ids[] = {
--
2.50.1