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Mon, 04 Aug 2025 02:36:11 -0700 (PDT) Date: Mon, 4 Aug 2025 12:36:09 +0300 From: Abel Vesa To: Taniya Das Cc: Konrad Dybcio , kernel@oss.qualcomm.com, Pankaj Patil , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 3/7] clk: qcom: Add TCSR clock driver for Glymur Message-ID: References: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-0-227cfe5c8ef4@oss.qualcomm.com> <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-3-227cfe5c8ef4@oss.qualcomm.com> <784545d0-2173-4a8b-9d5d-bee11226351e@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On 25-08-04 14:30:00, Taniya Das wrote: > > > On 8/1/2025 5:24 PM, Konrad Dybcio wrote: > > On 8/1/25 7:31 AM, Abel Vesa wrote: > >> On 25-08-01 10:02:15, Taniya Das wrote: > >>> > >>> > >>> On 7/30/2025 4:55 PM, Abel Vesa wrote: > >>>> On 25-07-29 11:12:37, Taniya Das wrote: > >>>>> Add a clock driver for the TCSR clock controller found on Glymur, which > >>>>> provides refclks for PCIE, USB, and UFS. > >>>>> > >>>>> Signed-off-by: Taniya Das > >>>>> --- > >>>>> drivers/clk/qcom/Kconfig | 8 ++ > >>>>> drivers/clk/qcom/Makefile | 1 + > >>>>> drivers/clk/qcom/tcsrcc-glymur.c | 257 +++++++++++++++++++++++++++++++++++++++ > >>>>> 3 files changed, 266 insertions(+) > >>>>> > >>>> > >>>> [...] > >>>> > >>>>> + > >>>>> +static struct clk_branch tcsr_edp_clkref_en = { > >>>>> + .halt_reg = 0x1c, > >>>>> + .halt_check = BRANCH_HALT_DELAY, > >>>>> + .clkr = { > >>>>> + .enable_reg = 0x1c, > >>>>> + .enable_mask = BIT(0), > >>>>> + .hw.init = &(const struct clk_init_data) { > >>>>> + .name = "tcsr_edp_clkref_en", > >>>>> + .ops = &clk_branch2_ops, > >>>> > >>>> As discussed off-list, these clocks need to have the bi_tcxo as parent. > >>>> > >>>> Otherwise, as far as the CCF is concerned these clocks will have rate 0, > >>>> which is obviously not the case. > >>>> > >>>> Bringing this here since there is a disconnect between X Elite and > >>>> Glymur w.r.t this now. > >>> > >>> > >>> The ref clocks are not required to be have a parent of bi_tcxo as these > >>> ideally can be left enabled(as a subsystem requirement) even if HLOS > >>> (APSS) goes to suspend. With the bi_tcxo parent the ARC vote from > >>> HLOS/APSS will not allow APSS to collapse. > >> > >> Is there a scenario where the APSS is collapsed and still the ref clock > >> needs to stay enabled ? Sorry, this doesn't make sense to me. > > > > MDSS is capable of displaying things from a buffer when the CPU is off, > > AFAICU > > > > We can do CXO_AO instead to have it auto-collapse if it's just Linux > > requesting it to stay on, I think. > > > > Thanks Konrad for adding the display use case. OK, that usecase makes sense then. > Abel, we earlier also had some PCIe, USB use cases where we had to leave > the ref clocks ON and APSS could collapse. Then we need to model that in a different way. Leaving those clocks without parents should not be the option. Maybe the CXO_AO is the best option then. > > > -- > Thanks, > Taniya Das >