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s=mail; t=1754483435; bh=mSYUh+T5LKyYNPZakKmsiXm0B30JrcVYTIzk5jrro4U=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=EW9IebddAIj6oJPaTxR3Luvi4SbR+tvpbpNMG4Xj3dp25aspX/Uy9BxH+402f6UaE Amy73reDlzOr7ogRTw8hdC/8nYocyT3fwYS+06foQVMca4qzGcPv+r6gTDSJjq8yz5 tJV4IHOyYZ7bKOn8tYLXdDXN17B1zEDlrypVJamaeuPwrYTvvXz0zFPdRgZqsq9qTQ e+IDPelK0nsSE42p4lWLeL2Ak0pOe6Wb8lLl6P2tNp9n67rluJtdgfLWrUUqP6gBAj 5eDP4HJNC/5YmisBT/FaBKOGvN8G1XNZSshtDlFdLxQ1aJU7arFmE+fxRQzStfjDJV yF3dYv5OFCsQg== Date: Wed, 6 Aug 2025 12:30:18 +0000 From: Yao Zi To: Huacai Chen Cc: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , WANG Xuerui , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit Subject: Re: [PATCH v3 1/8] dt-bindings: clock: loongson2: Add Loongson 2K0300 compatible Message-ID: References: <20250805150147.25909-1-ziyao@disroot.org> <20250805150147.25909-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Aug 06, 2025 at 04:36:50PM +0800, Huacai Chen wrote: > On Tue, Aug 5, 2025 at 11:03 PM Yao Zi wrote: > > > > Document the clock controller shipped in Loongson 2K0300 SoC, which > > generates various clock signals for SoC peripherals. > > > > Differing from previous generations of SoCs, 2K0300 requires a 120MHz > > external clock input, and a separate dt-binding header is used for > > cleanness. > > > > Signed-off-by: Yao Zi > > --- > > .../bindings/clock/loongson,ls2k-clk.yaml | 21 ++++++-- > > MAINTAINERS | 1 + > > .../dt-bindings/clock/loongson,ls2k0300-clk.h | 54 +++++++++++++++++++ > > 3 files changed, 72 insertions(+), 4 deletions(-) > > create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h > > ... > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 4912b8a83bbb..7960e65d7dfc 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -14365,6 +14365,7 @@ S: Maintained > > F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml > > F: drivers/clk/clk-loongson2.c > > F: include/dt-bindings/clock/loongson,ls2k-clk.h > > +F: include/dt-bindings/clock/loongson,ls2k0300-clk.h > I think ls2k0300-clk.h can be merged into ls2k-clk.h Honestly I think a separate header makes the purpose more clear, and follows the convention that name of binding header matches the compatible, but I'm willing to change if you really consider merging them together is better and dt-binding maintainer agrees on this. > Huacai Thanks, Yao Zi > > > > LOONGSON SPI DRIVER > > M: Yinbo Zhu > > diff --git a/include/dt-bindings/clock/loongson,ls2k0300-clk.h b/include/dt-bindings/clock/loongson,ls2k0300-clk.h > > new file mode 100644 > > index 000000000000..5e8f7b2f33f2 > > --- /dev/null > > +++ b/include/dt-bindings/clock/loongson,ls2k0300-clk.h > > @@ -0,0 +1,54 @@ > > +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ > > +/* > > + * Copyright (C) 2025 Yao Zi > > + */ > > +#ifndef _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ > > +#define _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ > > + > > +/* Derivied from REFCLK */ > > +#define LS2K0300_CLK_STABLE 0 > > +#define LS2K0300_PLL_NODE 1 > > +#define LS2K0300_PLL_DDR 2 > > +#define LS2K0300_PLL_PIX 3 > > +#define LS2K0300_CLK_THSENS 4 > > + > > +/* Derived from PLL_NODE */ > > +#define LS2K0300_CLK_NODE_DIV 5 > > +#define LS2K0300_CLK_NODE_PLL_GATE 6 > > +#define LS2K0300_CLK_NODE_SCALE 7 > > +#define LS2K0300_CLK_NODE_GATE 8 > > +#define LS2K0300_CLK_GMAC_DIV 9 > > +#define LS2K0300_CLK_GMAC_GATE 10 > > +#define LS2K0300_CLK_I2S_DIV 11 > > +#define LS2K0300_CLK_I2S_SCALE 12 > > +#define LS2K0300_CLK_I2S_GATE 13 > > + > > +/* Derived from PLL_DDR */ > > +#define LS2K0300_CLK_DDR_DIV 14 > > +#define LS2K0300_CLK_DDR_GATE 15 > > +#define LS2K0300_CLK_NET_DIV 16 > > +#define LS2K0300_CLK_NET_GATE 17 > > +#define LS2K0300_CLK_DEV_DIV 18 > > +#define LS2K0300_CLK_DEV_GATE 19 > > + > > +/* Derived from PLL_PIX */ > > +#define LS2K0300_CLK_PIX_DIV 20 > > +#define LS2K0300_CLK_PIX_PLL_GATE 21 > > +#define LS2K0300_CLK_PIX_SCALE 22 > > +#define LS2K0300_CLK_PIX_GATE 23 > > +#define LS2K0300_CLK_GMACBP_DIV 24 > > +#define LS2K0300_CLK_GMACBP_GATE 25 > > + > > +/* Derived from CLK_DEV */ > > +#define LS2K0300_CLK_USB_SCALE 26 > > +#define LS2K0300_CLK_USB_GATE 27 > > +#define LS2K0300_CLK_APB_SCALE 28 > > +#define LS2K0300_CLK_APB_GATE 29 > > +#define LS2K0300_CLK_BOOT_SCALE 30 > > +#define LS2K0300_CLK_BOOT_GATE 31 > > +#define LS2K0300_CLK_SDIO_SCALE 32 > > +#define LS2K0300_CLK_SDIO_GATE 33 > > + > > +#define LS2K0300_CLK_GMAC_IN 34 > > + > > +#endif // _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ > > -- > > 2.50.1 > > >