From: Frank Li <Frank.li@nxp.com>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-media@vger.kernel.org, Conor Dooley <conor+dt@kernel.org>,
Fabio Estevam <festevam@gmail.com>,
Inbaraj E <inbaraj.e@samsung.com>,
Isaac Scott <isaac.scott@ideasonboard.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Martin Kepplinger <martink@posteo.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh@kernel.org>,
Rui Miguel Silva <rmfrfs@gmail.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Purism Kernel Team <kernel@puri.sm>,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 05/13] media: imx-mipi-csis: Rename register macros to match reference manual
Date: Fri, 22 Aug 2025 10:10:39 -0400 [thread overview]
Message-ID: <aKh6X2vLWT68rVAb@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20250822002734.23516-6-laurent.pinchart@ideasonboard.com>
On Fri, Aug 22, 2025 at 03:27:25AM +0300, Laurent Pinchart wrote:
> The CSIS driver uses register macro names that do not match the
> reference manual of the i.MX7[DS] and i.MX8M[MNP] SoCs in which the CSIS
> is integrated. Rename them to match the documentation, making the code
> easier to read alongside the reference manuals.
>
> One of the misnamed register fields is MIPI_CSIS_INT_SRC_ERR_UNKNOWN,
> which led to the corresponding event being logged as "Unknown Error".
> The correct register field name is MIPI_CSIS_INT_SRC_ERR_ID, documented
> as "Unknown ID error". Update the event description accordingly.
>
> While at it, also replace a few *_OFFSET macros with parametric macros
> for consistency, and add the missing MIPI_CSIS_ISP_RESOL_VRESOL and
> MIPI_CSIS_ISP_RESOL_HRESOL register field macros.
>
> No functional change intended.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> Changes since v2:
>
> - Drop MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_NONE
> - Restore usage of BIT() for MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT
> ---
> drivers/media/platform/nxp/imx-mipi-csis.c | 68 +++++++++++-----------
> 1 file changed, 35 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/platform/nxp/imx-mipi-csis.c
> index 894d12fef519..ce889c436cb1 100644
> --- a/drivers/media/platform/nxp/imx-mipi-csis.c
> +++ b/drivers/media/platform/nxp/imx-mipi-csis.c
> @@ -55,13 +55,12 @@
> /* CSIS common control */
> #define MIPI_CSIS_CMN_CTRL 0x04
> #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16)
> -#define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10)
> +#define MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT BIT(10)
> +#define MIPI_CSIS_CMN_CTRL_LANE_NUMBER(n) ((n) << 8)
> +#define MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK (3 << 8)
> #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2)
> -#define MIPI_CSIS_CMN_CTRL_RESET BIT(1)
> -#define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0)
> -
> -#define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8
> -#define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8)
> +#define MIPI_CSIS_CMN_CTRL_SW_RESET BIT(1)
> +#define MIPI_CSIS_CMN_CTRL_CSI_EN BIT(0)
>
> /* CSIS clock control */
> #define MIPI_CSIS_CLK_CTRL 0x08
> @@ -87,7 +86,7 @@
> #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3)
> #define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2)
> #define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1)
> -#define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0)
> +#define MIPI_CSIS_INT_MSK_ERR_ID BIT(0)
>
> /* CSIS Interrupt source */
> #define MIPI_CSIS_INT_SRC 0x14
> @@ -107,7 +106,7 @@
> #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3)
> #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2)
> #define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1)
> -#define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0)
> +#define MIPI_CSIS_INT_SRC_ERR_ID BIT(0)
> #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff
>
> /* D-PHY status control */
> @@ -123,8 +122,8 @@
> #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24)
> #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22)
> #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22)
> -#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6)
> -#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5)
> +#define MIPI_CSIS_DPHY_CMN_CTRL_S_DPDN_SWAP_CLK BIT(6)
> +#define MIPI_CSIS_DPHY_CMN_CTRL_S_DPDN_SWAP_DAT BIT(5)
> #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1)
> #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0)
> #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0)
> @@ -179,21 +178,23 @@
> #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12)
> #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12)
> #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */
> -#define MIPI_CSIS_ISPCFG_PIXEL_MASK (3 << 12)
> -#define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11)
> -#define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2)
> -#define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2)
> +#define MIPI_CSIS_ISPCFG_PIXEL_MODE_MASK (3 << 12)
> +#define MIPI_CSIS_ISPCFG_PARALLEL BIT(11)
> +#define MIPI_CSIS_ISPCFG_DATAFORMAT(fmt) ((fmt) << 2)
> +#define MIPI_CSIS_ISPCFG_DATAFORMAT_MASK (0x3f << 2)
>
> /* ISP Image Resolution register */
> #define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10)
> +#define MIPI_CSIS_ISP_RESOL_VRESOL(n) ((n) << 16)
> +#define MIPI_CSIS_ISP_RESOL_HRESOL(n) ((n) << 0)
> #define CSIS_MAX_PIX_WIDTH 0xffff
> #define CSIS_MAX_PIX_HEIGHT 0xffff
>
> /* ISP SYNC register */
> #define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10)
> -#define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18
> -#define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12
> -#define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0
> +#define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV(n) ((n) << 18)
> +#define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV(n) ((n) << 12)
> +#define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV(n) ((n) << 0)
>
> /* ISP shadow registers */
> #define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10)
> @@ -246,7 +247,7 @@ static const struct mipi_csis_event mipi_csis_events[] = {
> { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" },
> { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" },
> { false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" },
> - { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" },
> + { false, MIPI_CSIS_INT_SRC_ERR_ID, "Unknown ID Error" },
> { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" },
> { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" },
> { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" },
> @@ -517,7 +518,7 @@ static void mipi_csis_sw_reset(struct mipi_csis_device *csis)
> u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
>
> mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
> - val | MIPI_CSIS_CMN_CTRL_RESET);
> + val | MIPI_CSIS_CMN_CTRL_SW_RESET);
> usleep_range(10, 20);
> }
>
> @@ -527,9 +528,9 @@ static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on)
>
> val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
> if (on)
> - val |= MIPI_CSIS_CMN_CTRL_ENABLE;
> + val |= MIPI_CSIS_CMN_CTRL_CSI_EN;
> else
> - val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
> + val &= ~MIPI_CSIS_CMN_CTRL_CSI_EN;
> mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
>
> val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL);
> @@ -549,8 +550,8 @@ static void __mipi_csis_set_format(struct mipi_csis_device *csis,
>
> /* Color format */
> val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0));
> - val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK
> - | MIPI_CSIS_ISPCFG_PIXEL_MASK);
> + val &= ~(MIPI_CSIS_ISPCFG_PARALLEL | MIPI_CSIS_ISPCFG_PIXEL_MODE_MASK |
> + MIPI_CSIS_ISPCFG_DATAFORMAT_MASK);
>
> /*
> * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample
> @@ -568,12 +569,13 @@ static void __mipi_csis_set_format(struct mipi_csis_device *csis,
> if (csis_fmt->data_type == MIPI_CSI2_DT_YUV422_8B)
> val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL;
>
> - val |= MIPI_CSIS_ISPCFG_FMT(csis_fmt->data_type);
> + val |= MIPI_CSIS_ISPCFG_DATAFORMAT(csis_fmt->data_type);
> mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val);
>
> /* Pixel resolution */
> - val = format->width | (format->height << 16);
> - mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val);
> + mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0),
> + MIPI_CSIS_ISP_RESOL_VRESOL(format->height) |
> + MIPI_CSIS_ISP_RESOL_HRESOL(format->width));
> }
>
> static int mipi_csis_calculate_params(struct mipi_csis_device *csis,
> @@ -633,10 +635,10 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
> u32 val;
>
> val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
> - val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
> - val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
> + val &= ~MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK;
> + val |= MIPI_CSIS_CMN_CTRL_LANE_NUMBER(lanes - 1);
> if (csis->info->version == MIPI_CSIS_V3_3)
> - val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
> + val |= MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT;
> mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
>
> __mipi_csis_set_format(csis, format, csis_fmt);
> @@ -645,10 +647,10 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
> MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) |
> MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle));
>
> - val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
> - | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
> - | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
> - mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val);
> + mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0),
> + MIPI_CSIS_ISP_SYNC_HSYNC_LINTV(0) |
> + MIPI_CSIS_ISP_SYNC_VSYNC_SINTV(0) |
> + MIPI_CSIS_ISP_SYNC_VSYNC_EINTV(0));
>
> val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
> val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
> --
> Regards,
>
> Laurent Pinchart
>
next prev parent reply other threads:[~2025-08-22 14:10 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-22 0:27 [PATCH v3 00/13] media: imx-mipi-csis: Cleanups and debugging improvements Laurent Pinchart
2025-08-22 0:27 ` [PATCH v3 01/13] media: v4l2-common: Constify media_pad argument to v4l2_get_link_freq() Laurent Pinchart
2025-08-22 0:27 ` [PATCH v3 02/13] media: imx-mipi-csis: Simplify access to source pad Laurent Pinchart
2025-08-22 0:27 ` [PATCH v3 03/13] media: imx-mipi-csis: Standardize const keyword placement Laurent Pinchart
2025-08-22 0:27 ` [PATCH v3 04/13] media: imx-mipi-csis: Shorten name of subdev state variables Laurent Pinchart
2025-08-22 0:27 ` [PATCH v3 05/13] media: imx-mipi-csis: Rename register macros to match reference manual Laurent Pinchart
2025-08-22 14:10 ` Frank Li [this message]
2025-08-22 0:27 ` [PATCH v3 06/13] media: imx-mipi-csis: Use GENMASK for all register field masks Laurent Pinchart
2025-08-22 14:13 ` Frank Li
2025-08-22 14:40 ` Laurent Pinchart
2025-08-22 14:47 ` Frank Li
2025-08-22 0:27 ` [PATCH v3 07/13] media: imx-mipi-csis: Fix field alignment in register dump Laurent Pinchart
2025-08-22 0:27 ` [PATCH v3 08/13] media: imx-mipi-csis: Log per-lane start of transmission errors Laurent Pinchart
2025-08-22 0:27 ` [PATCH v3 09/13] media: imx-mipi-csis: Only set clock rate when specified in DT Laurent Pinchart
2025-08-22 0:27 ` [PATCH v3 10/13] dt-bindings: media: nxp,imx-mipi-csi2: Mark clock-frequency as deprecated Laurent Pinchart
2025-08-22 0:27 ` [PATCH v3 11/13] dt-bindings: media: nxp,imx-mipi-csi2: Add fsl,num-channels property Laurent Pinchart
2025-08-22 0:27 ` [PATCH v3 12/13] media: imx-mipi-csis: Initial support for multiple output channels Laurent Pinchart
2025-08-22 14:12 ` Stefan Klug
2025-08-22 20:08 ` Laurent Pinchart
2025-08-22 21:15 ` Stefan Klug
2025-08-22 14:18 ` Frank Li
2025-08-22 17:39 ` Laurent Pinchart
2025-08-22 0:27 ` [PATCH v3 13/13] arm64: dts: imx8mp: Specify the number of channels for CSI-2 receivers Laurent Pinchart
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aKh6X2vLWT68rVAb@lizhi-Precision-Tower-5810 \
--to=frank.li@nxp.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=imx@lists.linux.dev \
--cc=inbaraj.e@samsung.com \
--cc=isaac.scott@ideasonboard.com \
--cc=kernel@pengutronix.de \
--cc=kernel@puri.sm \
--cc=krzk+dt@kernel.org \
--cc=laurent.pinchart@ideasonboard.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-media@vger.kernel.org \
--cc=martink@posteo.de \
--cc=mchehab@kernel.org \
--cc=rmfrfs@gmail.com \
--cc=robh@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=shawnguo@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).