From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-171.mta0.migadu.com (out-171.mta0.migadu.com [91.218.175.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C96EC29A2 for ; Sun, 7 Sep 2025 13:12:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.171 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757250760; cv=none; b=aVxGte+qEE50Dspphl1D4dbLpy4vvDVI/Ue+wHECrnvxJRlrfVf8YreXuHaTZ4kpzqMifKHksHvEtSov/2vGAHQCjIjwY+ie8QGVU+BB3QQ8si70CI3l1HDtbC2SBIIsp0hryYZufV3Ffvh0Q67Kj7BLc44J0J+e2Jdw0srr7bw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757250760; c=relaxed/simple; bh=nG5wetaJQPoFOgX2jI1XYan+GC+3MW+xi5ekXTnU0OM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=cBg1k5cuD0R4pydfEk6tbUWr3aOo1j2EbyRNEj/uJPoF0qceeL5xzhIxXnbb4ofBO12ODFVgKDFIo93jGDsqgbQiQ1jiiK7jIzBXTLPVV8w1HGhoRm/08/yUSFTMBp0OAjgHhGoDQA6Js/ftYE9xh+vaPsKXdU3XomIJPMO9pas= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=rosenzweig.io; spf=pass smtp.mailfrom=rosenzweig.io; dkim=pass (2048-bit key) header.d=rosenzweig.io header.i=@rosenzweig.io header.b=Xa1Qe31i; arc=none smtp.client-ip=91.218.175.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=rosenzweig.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rosenzweig.io Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rosenzweig.io header.i=@rosenzweig.io header.b="Xa1Qe31i" Date: Sun, 7 Sep 2025 09:12:29 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rosenzweig.io; s=key1; t=1757250755; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=c6m2JvKKQLislbG/lLsCQpWLwDoRY8Pnbo43WEoeMe4=; b=Xa1Qe31ib2MbCn8EA7bchWhfdlA69tFg5z35UwJQfmd/Y+tD/PnIaII2ok+/cGbmnaygXG cnw0y5r7Lms2YbuHpkXTnZCsUwBRzmNUq0k2vkecwSzbffFAP5DJB/cgPz2kYUDhWVQydd MxpBtCD9cBLbhBTqvlClPvOT+OV0rOM3rCofbu3hXvPlLJDNFiPdeWMyrU+CCuBkmMtoaw Gtga+xNV4nk42xOEzsnqV6FeJAZ86ROd+Y12UL15xy8xQYr4FlA62dk47mPE1AdKArv3Ag aSPKmGr8VWm5B50+e1c/3HddNFZeSixDBFM38iHoz+QSwegkhGRdJDD4gc2PDQ== X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Alyssa Anne Rosenzweig To: Sven Peter Cc: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel , Frank Li , Ran Wang , Peter Chen , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Hector Martin Subject: Re: [PATCH v2 18/22] phy: apple: Add Apple Type-C PHY Message-ID: References: <20250906-atcphy-6-17-v2-0-52c348623ef6@kernel.org> <20250906-atcphy-6-17-v2-18-52c348623ef6@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250906-atcphy-6-17-v2-18-52c348623ef6@kernel.org> X-Migadu-Flow: FLOW_OUT Looks a lot nicer than the initial version I looked at a few months ago, nice work Sven :-) If we're going to define all those mask32/clear32/etc convenience helpers, there are a couple more we should probably add and use too: 1. void cond_set32(void __iomem *reg, bool cond, u32 mask) { if (cond) { set32(reg, mask); } else { clear32(reg, mask); } } Not sure on the name but this shows up a bunch of places and turns messy sequences into straight-line code at least. 2. #define bit_to_OV(reg, bit) \ clear32(reg, bit); \ set32(reg, bit ## _OV); \ Also not sure on the name, but this would make a bunch of sequences more compact. For example > clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST); > set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_OV); > clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_2R); > set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_2R_OV); > clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_4R); > set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_4R_OV); > clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE); > set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_OV); > clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_2R); > set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_2R_OV); > clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_4R); > set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_4R_OV); turns into > bit_to_OV(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST); > bit_to_OV(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_2R); > bit_to_OV(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_4R); > bit_to_OV(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE); > bit_to_OV(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_2R); > bit_to_OV(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_4R); 3. static inline const struct atcphy_mode_configuration *get_mode_cfg(struct apple_atcphy *atcphy, enum atcphy_mode) { if (atcphy->swap_lanes) return &atcphy_modes[mode].swapped; else return &atcphy_modes[mode].normal; } This only shows up two places but both would be improved by its use. --- With those cleanups (or an explanation why they're silly), ttbomk this is r-b me, thank you!