From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F16032D480E for ; Mon, 8 Sep 2025 19:52:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757361149; cv=none; b=KyeSQreTqHh1Gs37uJ11PSMGWeWok/d460dh3UiyBlfYZsPrn5MwTzoIyxftnfUzsQ89b0uIpDRmGsI343zjt6iI0c6RLbkljFQhfypfLdPreg9+f4Mfu8OScLhVQREEpSkrHhlPeI7/BNxPN+ntNzhV6J0eaWGUFGBdrkDuwE0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757361149; c=relaxed/simple; bh=KG/wZiINb4q+y6OBOElz2J9sgATSOMqPoUnV+iOCiIA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=q5RRf8tAcJG1DydBUd30ZK/+bnIzFjZYdtELATSnQyVg41fr6Ka3/12NAMfj2w22b5cZXk/oCSHTchSCOyEgwKkm8Oqn6sEwuWvVGszdynxnTbrxX/RcMbOViBeLk5wucUx8lQpggAbx5Nw2jwHbbQBKPqdWXz7OOk8TyB12rrA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B4ED41692 for ; Mon, 8 Sep 2025 12:52:17 -0700 (PDT) Received: from e110455-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CFBF13F694 for ; Mon, 8 Sep 2025 12:52:25 -0700 (PDT) Date: Mon, 8 Sep 2025 20:51:58 +0100 From: Liviu Dudau To: Nicolas Frattaroli Cc: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" , Chia-I Wu , Chen-Yu Tsai , kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org Subject: Re: [PATCH RFC 01/10] dt-bindings: gpu: mali-valhall-csf: add mediatek,mt8196-mali variant Message-ID: References: <20250905-mt8196-gpufreq-v1-0-7b6c2d6be221@collabora.com> <20250905-mt8196-gpufreq-v1-1-7b6c2d6be221@collabora.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250905-mt8196-gpufreq-v1-1-7b6c2d6be221@collabora.com> On Fri, Sep 05, 2025 at 12:22:57PM +0200, Nicolas Frattaroli wrote: > The Mali-based GPU on the MediaTek MT8196 SoC is shackled to its concept > of "MFlexGraphics", which in this iteration includes an embedded MCU > that needs to be poked to power on the GPU, and is in charge of > controlling all the clocks and regulators. > > In return, it lets us omit the OPP tables from the device tree, as those > can now be enumerated at runtime from the MCU. > > Add the mediatek,mt8196-mali compatible, and a performance-controller > property which points to a node representing such setups. It's required > on mt8196 devices. > > Signed-off-by: Nicolas Frattaroli > --- > .../bindings/gpu/arm,mali-valhall-csf.yaml | 36 +++++++++++++++++++++- > 1 file changed, 35 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > index a5b4e00217587c5d1f889094e2fff7b76e6148eb..6df802e900b744d226395c29f8d87fb6d3282d26 100644 > --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > @@ -19,6 +19,7 @@ properties: > - items: > - enum: > - rockchip,rk3588-mali > + - mediatek,mt8196-mali > - const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable > > reg: > @@ -53,6 +54,13 @@ properties: > opp-table: > type: object > > + performance-controller: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + A phandle of a device that controls this GPU's power and frequency, > + if any. If present, this is usually in the form of some specialised > + embedded MCU. > + > power-domains: > minItems: 1 > maxItems: 5 > @@ -91,7 +99,6 @@ required: > - interrupts > - interrupt-names > - clocks > - - mali-supply > > additionalProperties: false > > @@ -105,9 +112,24 @@ allOf: > properties: > clocks: > minItems: 3 > + performance-controller: false > power-domains: > maxItems: 1 > power-domain-names: false > + required: > + - mali-supply > + - if: > + properties: > + compatible: > + contains: > + const: rockchip,mt8196-mali s/rockchip/mediatek/ Best regards, Liviu > + then: > + properties: > + mali-supply: false > + sram-supply: false > + operating-points-v2: false > + required: > + - performance-controller > > examples: > - | > @@ -143,5 +165,17 @@ examples: > }; > }; > }; > + - | > + gpu2: gpu@48000000 { > + compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf"; > + reg = <0x48000000 0x480000>; > + clocks = <&mfgpll 0>; > + clock-names = "core"; > + interrupts = , > + , > + ; > + interrupt-names = "job", "mmu", "gpu"; > + performance-controller = <&gpufreq>; > + }; > > ... > > -- > 2.51.0 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ¯\_(ツ)_/¯