[PATCH v2 0/9] spi: spi-fsl-lpspi: Generic fixes and support for S32G devices

[PATCH v2 0/9] spi: spi-fsl-lpspi: Generic fixes and support for S32G devices

[James Clark]

Various fixes for LPSI along with some refactorings. None of the fixes
are strictly related to S32G, however these changes all originate from
the work to support S32G devices. The only commits that are strictly
related are for the new s32g2 and s32g3 compatible strings.

Signed-off-by: James Clark <james.clark@linaro.org>
---
To: Frank Li <Frank.Li@nxp.com>
To: Mark Brown <broonie@kernel.org>
To: Clark Wang <xiaoning.wang@nxp.com>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Shawn Guo <shawnguo@kernel.org>
To: Sascha Hauer <s.hauer@pengutronix.de>
To: Fabio Estevam <festevam@gmail.com>
To: Larisa Grigore <larisa.grigore@oss.nxp.com>
To: Larisa Grigore <larisa.grigore@nxp.com>
To: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
To: Ciprianmarian Costea <ciprianmarian.costea@nxp.com>
To: s32@nxp.com
Cc: linux-spi@vger.kernel.org
Cc: imx@lists.linux.dev
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org

---
Changes in v2:
- Drop changes to be able to swap input/output pins. It's not required
  for generic S32G support and we don't know what board it's for.
- Drop binding change for max num_cs value. Although the maximum is 3,
  this would be autodetected so it should be left blank. 2 is the max
  that is required to set manually.
- Fix missing bitfield header for some compile targets
- Keep prescale_max as a numeric value, but treat 0 as no limit
- Put compatible string dt-bindings patch before driver change
- Link to v1: https://lore.kernel.org/r/20250814-james-nxp-lpspi-v1-0-9586d7815d14@linaro.org

---
James Clark (3):
      spi: spi-fsl-lpspi: Constify devtype datas
      spi: spi-fsl-lpspi: Treat prescale_max == 0 as no erratum
      spi: spi-fsl-lpspi: Parameterize reading num-cs from hardware

Larisa Grigore (6):
      spi: spi-fsl-lpspi: Fix transmissions when using CONT
      spi: spi-fsl-lpspi: Set correct chip-select polarity bit
      spi: spi-fsl-lpspi: Reset FIFO and disable module on transfer abort
      spi: spi-fsl-lpspi: Clear status register after disabling the module
      dt-bindings: lpspi: Document support for S32G
      spi: spi-fsl-lpspi: Add compatible for S32G

 .../devicetree/bindings/spi/spi-fsl-lpspi.yaml     |  5 +++
 drivers/spi/spi-fsl-lpspi.c                        | 47 +++++++++++++---------
 2 files changed, 33 insertions(+), 19 deletions(-)
---
base-commit: 07d9df80082b8d1f37e05658371b087cb6738770
change-id: 20250715-james-nxp-lpspi-1fac58e72a59

Best regards,
-- 
James Clark <james.clark@linaro.org>

[PATCH v2 1/9] spi: spi-fsl-lpspi: Fix transmissions when using CONT

[James Clark]

From: Larisa Grigore <larisa.grigore@nxp.com>

Commit 6a130448498c ("spi: lpspi: Fix wrong transmission when don't use
CONT") breaks transmissions when CONT is used. The TDIE interrupt should
not be disabled in all cases. If CONT is used and the TX transfer is not
yet completed yet, but the interrupt handler is called because there are
characters to be received, TDIE is replaced with FCIE. When the transfer
is finally completed, SR_TDF is set but the interrupt handler isn't
called again.

Fixes: 6a130448498c ("spi: lpspi: Fix wrong transmission when don't use CONT")
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
 drivers/spi/spi-fsl-lpspi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index 313e444a34f3..eaa6bade61a6 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -3,7 +3,7 @@
 // Freescale i.MX7ULP LPSPI driver
 //
 // Copyright 2016 Freescale Semiconductor, Inc.
-// Copyright 2018 NXP Semiconductors
+// Copyright 2018, 2023, 2025 NXP
 
 #include <linux/clk.h>
 #include <linux/completion.h>
@@ -785,7 +785,7 @@ static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
 	if (temp_SR & SR_MBF ||
 	    readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
 		writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
-		fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
+		fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE | (temp_IER & IER_TDIE));
 		return IRQ_HANDLED;
 	}
 

-- 
2.34.1

[PATCH v2 2/9] spi: spi-fsl-lpspi: Set correct chip-select polarity bit

[James Clark]

From: Larisa Grigore <larisa.grigore@nxp.com>

The driver currently supports multiple chip-selects, but only sets the
polarity for the first one (CS 0). Fix it by setting the PCSPOL bit for
the desired chip-select.

Fixes: 5314987de5e5 ("spi: imx: add lpspi bus driver")
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
 drivers/spi/spi-fsl-lpspi.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index eaa6bade61a6..5ea4a306ffa6 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -5,6 +5,7 @@
 // Copyright 2016 Freescale Semiconductor, Inc.
 // Copyright 2018, 2023, 2025 NXP
 
+#include <linux/bitfield.h>
 #include <linux/clk.h>
 #include <linux/completion.h>
 #include <linux/delay.h>
@@ -70,7 +71,7 @@
 #define DER_TDDE	BIT(0)
 #define CFGR1_PCSCFG	BIT(27)
 #define CFGR1_PINCFG	(BIT(24)|BIT(25))
-#define CFGR1_PCSPOL	BIT(8)
+#define CFGR1_PCSPOL_MASK	GENMASK(11, 8)
 #define CFGR1_NOSTALL	BIT(3)
 #define CFGR1_HOST	BIT(0)
 #define FSR_TXCOUNT	(0xFF)
@@ -423,7 +424,9 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
 	else
 		temp = CFGR1_PINCFG;
 	if (fsl_lpspi->config.mode & SPI_CS_HIGH)
-		temp |= CFGR1_PCSPOL;
+		temp |= FIELD_PREP(CFGR1_PCSPOL_MASK,
+				   BIT(fsl_lpspi->config.chip_select));
+
 	writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
 
 	temp = readl(fsl_lpspi->base + IMX7ULP_CR);

-- 
2.34.1

[PATCH v2 3/9] spi: spi-fsl-lpspi: Reset FIFO and disable module on transfer abort

[James Clark]

From: Larisa Grigore <larisa.grigore@nxp.com>

In DMA mode fsl_lpspi_reset() is always called at the end, even when the
transfer is aborted. In PIO mode aborts skip the reset leaving the FIFO
filled and the module enabled.

Fix it by always calling fsl_lpspi_reset().

Fixes: a15dc3d657fa ("spi: lpspi: Fix CLK pin becomes low before one transfer")
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
 drivers/spi/spi-fsl-lpspi.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index 5ea4a306ffa6..e50261e9a1fa 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -733,12 +733,10 @@ static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
 	fsl_lpspi_write_tx_fifo(fsl_lpspi);
 
 	ret = fsl_lpspi_wait_for_completion(controller);
-	if (ret)
-		return ret;
 
 	fsl_lpspi_reset(fsl_lpspi);
 
-	return 0;
+	return ret;
 }
 
 static int fsl_lpspi_transfer_one(struct spi_controller *controller,

-- 
2.34.1

[PATCH v2 4/9] spi: spi-fsl-lpspi: Clear status register after disabling the module

[James Clark]

From: Larisa Grigore <larisa.grigore@nxp.com>

Clear the error flags after disabling the module to avoid the case when
a flag is set again between flag clear and module disable. And use
SR_CLEAR_MASK to replace hardcoded value for improved readability.

Although fsl_lpspi_reset() was only introduced in commit a15dc3d657fa
("spi: lpspi: Fix CLK pin becomes low before one transfer"), the
original driver only reset SR in the interrupt handler, making it
vulnerable to the same issue. Therefore the fixes commit is set at the
introduction of the driver.

Fixes: 5314987de5e5 ("spi: imx: add lpspi bus driver")
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
 drivers/spi/spi-fsl-lpspi.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index e50261e9a1fa..fc4d49f0717e 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -83,6 +83,8 @@
 #define TCR_RXMSK	BIT(19)
 #define TCR_TXMSK	BIT(18)
 
+#define SR_CLEAR_MASK	GENMASK(13, 8)
+
 struct fsl_lpspi_devtype_data {
 	u8 prescale_max;
 };
@@ -535,14 +537,13 @@ static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
 		fsl_lpspi_intctrl(fsl_lpspi, 0);
 	}
 
-	/* W1C for all flags in SR */
-	temp = 0x3F << 8;
-	writel(temp, fsl_lpspi->base + IMX7ULP_SR);
-
 	/* Clear FIFO and disable module */
 	temp = CR_RRF | CR_RTF;
 	writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 
+	/* W1C for all flags in SR */
+	writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR);
+
 	return 0;
 }
 

-- 
2.34.1

[PATCH v2 5/9] dt-bindings: lpspi: Document support for S32G

[James Clark]

From: Larisa Grigore <larisa.grigore@nxp.com>

Add compatible strings 'nxp,s32g2-lpspi' and 'nxp,s32g3-lpspi' for S32G2
and S32G3. Require nxp,s32g3-lpspi to fallback to nxp,s32g2-lpspi since
they are currently compatible.

Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
 Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
index a65a42ccaafe..a82360bed188 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
@@ -20,6 +20,7 @@ properties:
       - enum:
           - fsl,imx7ulp-spi
           - fsl,imx8qxp-spi
+          - nxp,s32g2-lpspi
       - items:
           - enum:
               - fsl,imx8ulp-spi
@@ -27,6 +28,10 @@ properties:
               - fsl,imx94-spi
               - fsl,imx95-spi
           - const: fsl,imx7ulp-spi
+      - items:
+          - const: nxp,s32g3-lpspi
+          - const: nxp,s32g2-lpspi
+
   reg:
     maxItems: 1
 

-- 
2.34.1

[PATCH v2 6/9] spi: spi-fsl-lpspi: Constify devtype datas

[James Clark]

Add const for all devtype_data.

Signed-off-by: James Clark <james.clark@linaro.org>
---
 drivers/spi/spi-fsl-lpspi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index fc4d49f0717e..f16449cf42bb 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -135,11 +135,11 @@ struct fsl_lpspi_data {
  * ERR051608 fixed or not:
  * https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf
  */
-static struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
+static const struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
 	.prescale_max = 1,
 };
 
-static struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
+static const struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
 	.prescale_max = 7,
 };
 

-- 
2.34.1

[PATCH v2 7/9] spi: spi-fsl-lpspi: Treat prescale_max == 0 as no erratum

[James Clark]

This erratum only ever results in a max value of 1, otherwise the full 3
bits are available. To avoid repeating the same default prescale value
for every new device's devdata, treat 0 as no limit (7) and only set a
value when the erratum is present.

Change the field to be 3 bits to catch out of range definitions.

No functionality change.

Signed-off-by: James Clark <james.clark@linaro.org>
---
 drivers/spi/spi-fsl-lpspi.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index f16449cf42bb..ea25e8dab0a4 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -86,7 +86,7 @@
 #define SR_CLEAR_MASK	GENMASK(13, 8)
 
 struct fsl_lpspi_devtype_data {
-	u8 prescale_max;
+	u8 prescale_max : 3; /* 0 == no limit */
 };
 
 struct lpspi_config {
@@ -132,15 +132,15 @@ struct fsl_lpspi_data {
 };
 
 /*
- * ERR051608 fixed or not:
- * https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf
+ * Devices with ERR051608 have a max TCR_PRESCALE value of 1, otherwise there is
+ * no prescale limit: https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf
  */
 static const struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
 	.prescale_max = 1,
 };
 
 static const struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
-	.prescale_max = 7,
+	/* All defaults */
 };
 
 static const struct of_device_id fsl_lpspi_dt_ids[] = {
@@ -324,7 +324,7 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
 	int scldiv;
 
 	perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
-	prescale_max = fsl_lpspi->devtype_data->prescale_max;
+	prescale_max = fsl_lpspi->devtype_data->prescale_max ?: 7;
 
 	if (!config.speed_hz) {
 		dev_err(fsl_lpspi->dev,

-- 
2.34.1

[PATCH v2 8/9] spi: spi-fsl-lpspi: Parameterize reading num-cs from hardware

[James Clark]

Add query_hw_for_num_cs in devtype to avoid directly checking compatible
string "fsl,imx93-spi".

No functionality change.

Signed-off-by: James Clark <james.clark@linaro.org>
---
 drivers/spi/spi-fsl-lpspi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index ea25e8dab0a4..ce347cdbb009 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -87,6 +87,7 @@
 
 struct fsl_lpspi_devtype_data {
 	u8 prescale_max : 3; /* 0 == no limit */
+	bool query_hw_for_num_cs : 1;
 };
 
 struct lpspi_config {
@@ -137,6 +138,7 @@ struct fsl_lpspi_data {
  */
 static const struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
 	.prescale_max = 1,
+	.query_hw_for_num_cs = true,
 };
 
 static const struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
@@ -932,7 +934,7 @@ static int fsl_lpspi_probe(struct platform_device *pdev)
 	fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
 	if (of_property_read_u32((&pdev->dev)->of_node, "num-cs",
 				 &num_cs)) {
-		if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx93-spi"))
+		if (devtype_data->query_hw_for_num_cs)
 			num_cs = ((temp >> 16) & 0xf);
 		else
 			num_cs = 1;

-- 
2.34.1

[PATCH v2 9/9] spi: spi-fsl-lpspi: Add compatible for S32G

[James Clark]

From: Larisa Grigore <larisa.grigore@nxp.com>

S32G doesn't have the max prescale erratum (default) and it can query
the max number of CS from hardware, so add those settings.

Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
 drivers/spi/spi-fsl-lpspi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index ce347cdbb009..431439d4cdda 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -145,9 +145,14 @@ static const struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
 	/* All defaults */
 };
 
+static const struct fsl_lpspi_devtype_data s32g_lpspi_devtype_data = {
+	.query_hw_for_num_cs = true,
+};
+
 static const struct of_device_id fsl_lpspi_dt_ids[] = {
 	{ .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
 	{ .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
+	{ .compatible = "nxp,s32g2-lpspi", .data = &s32g_lpspi_devtype_data,},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);

-- 
2.34.1

Re: [PATCH v2 2/9] spi: spi-fsl-lpspi: Set correct chip-select polarity bit

[Frank Li]

On Thu, Aug 28, 2025 at 11:14:41AM +0100, James Clark wrote:
> From: Larisa Grigore <larisa.grigore@nxp.com>
>
> The driver currently supports multiple chip-selects, but only sets the
> polarity for the first one (CS 0). Fix it by setting the PCSPOL bit for
> the desired chip-select.
>
> Fixes: 5314987de5e5 ("spi: imx: add lpspi bus driver")
> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: James Clark <james.clark@linaro.org>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
>  drivers/spi/spi-fsl-lpspi.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
> index eaa6bade61a6..5ea4a306ffa6 100644
> --- a/drivers/spi/spi-fsl-lpspi.c
> +++ b/drivers/spi/spi-fsl-lpspi.c
> @@ -5,6 +5,7 @@
>  // Copyright 2016 Freescale Semiconductor, Inc.
>  // Copyright 2018, 2023, 2025 NXP
>
> +#include <linux/bitfield.h>
>  #include <linux/clk.h>
>  #include <linux/completion.h>
>  #include <linux/delay.h>
> @@ -70,7 +71,7 @@
>  #define DER_TDDE	BIT(0)
>  #define CFGR1_PCSCFG	BIT(27)
>  #define CFGR1_PINCFG	(BIT(24)|BIT(25))
> -#define CFGR1_PCSPOL	BIT(8)
> +#define CFGR1_PCSPOL_MASK	GENMASK(11, 8)
>  #define CFGR1_NOSTALL	BIT(3)
>  #define CFGR1_HOST	BIT(0)
>  #define FSR_TXCOUNT	(0xFF)
> @@ -423,7 +424,9 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
>  	else
>  		temp = CFGR1_PINCFG;
>  	if (fsl_lpspi->config.mode & SPI_CS_HIGH)
> -		temp |= CFGR1_PCSPOL;
> +		temp |= FIELD_PREP(CFGR1_PCSPOL_MASK,
> +				   BIT(fsl_lpspi->config.chip_select));
> +
>  	writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
>
>  	temp = readl(fsl_lpspi->base + IMX7ULP_CR);
>
> --
> 2.34.1
>

Re: [PATCH v2 5/9] dt-bindings: lpspi: Document support for S32G

[Frank Li]

On Thu, Aug 28, 2025 at 11:14:44AM +0100, James Clark wrote:
> From: Larisa Grigore <larisa.grigore@nxp.com>
>
> Add compatible strings 'nxp,s32g2-lpspi' and 'nxp,s32g3-lpspi' for S32G2
> and S32G3. Require nxp,s32g3-lpspi to fallback to nxp,s32g2-lpspi since
> they are currently compatible.
>
> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: James Clark <james.clark@linaro.org>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
>  Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
> index a65a42ccaafe..a82360bed188 100644
> --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
> @@ -20,6 +20,7 @@ properties:
>        - enum:
>            - fsl,imx7ulp-spi
>            - fsl,imx8qxp-spi
> +          - nxp,s32g2-lpspi
>        - items:
>            - enum:
>                - fsl,imx8ulp-spi
> @@ -27,6 +28,10 @@ properties:
>                - fsl,imx94-spi
>                - fsl,imx95-spi
>            - const: fsl,imx7ulp-spi
> +      - items:
> +          - const: nxp,s32g3-lpspi
> +          - const: nxp,s32g2-lpspi
> +
>    reg:
>      maxItems: 1
>
>
> --
> 2.34.1
>

Re: [PATCH v2 6/9] spi: spi-fsl-lpspi: Constify devtype datas

[Frank Li]

On Thu, Aug 28, 2025 at 11:14:45AM +0100, James Clark wrote:
> Add const for all devtype_data.
>
> Signed-off-by: James Clark <james.clark@linaro.org>

Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  drivers/spi/spi-fsl-lpspi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
> index fc4d49f0717e..f16449cf42bb 100644
> --- a/drivers/spi/spi-fsl-lpspi.c
> +++ b/drivers/spi/spi-fsl-lpspi.c
> @@ -135,11 +135,11 @@ struct fsl_lpspi_data {
>   * ERR051608 fixed or not:
>   * https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf
>   */
> -static struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
> +static const struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
>  	.prescale_max = 1,
>  };
>
> -static struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
> +static const struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
>  	.prescale_max = 7,
>  };
>
>
> --
> 2.34.1
>

Re: [PATCH v2 7/9] spi: spi-fsl-lpspi: Treat prescale_max == 0 as no erratum

[Frank Li]

On Thu, Aug 28, 2025 at 11:14:46AM +0100, James Clark wrote:
> This erratum only ever results in a max value of 1, otherwise the full 3
> bits are available. To avoid repeating the same default prescale value
> for every new device's devdata, treat 0 as no limit (7) and only set a
> value when the erratum is present.
>
> Change the field to be 3 bits to catch out of range definitions.
>
> No functionality change.
>
> Signed-off-by: James Clark <james.clark@linaro.org>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>
>  drivers/spi/spi-fsl-lpspi.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
> index f16449cf42bb..ea25e8dab0a4 100644
> --- a/drivers/spi/spi-fsl-lpspi.c
> +++ b/drivers/spi/spi-fsl-lpspi.c
> @@ -86,7 +86,7 @@
>  #define SR_CLEAR_MASK	GENMASK(13, 8)
>
>  struct fsl_lpspi_devtype_data {
> -	u8 prescale_max;
> +	u8 prescale_max : 3; /* 0 == no limit */
>  };
>
>  struct lpspi_config {
> @@ -132,15 +132,15 @@ struct fsl_lpspi_data {
>  };
>
>  /*
> - * ERR051608 fixed or not:
> - * https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf
> + * Devices with ERR051608 have a max TCR_PRESCALE value of 1, otherwise there is
> + * no prescale limit: https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf
>   */
>  static const struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
>  	.prescale_max = 1,
>  };
>
>  static const struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
> -	.prescale_max = 7,
> +	/* All defaults */
>  };
>
>  static const struct of_device_id fsl_lpspi_dt_ids[] = {
> @@ -324,7 +324,7 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
>  	int scldiv;
>
>  	perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
> -	prescale_max = fsl_lpspi->devtype_data->prescale_max;
> +	prescale_max = fsl_lpspi->devtype_data->prescale_max ?: 7;
>
>  	if (!config.speed_hz) {
>  		dev_err(fsl_lpspi->dev,
>
> --
> 2.34.1
>

Re: [PATCH v2 8/9] spi: spi-fsl-lpspi: Parameterize reading num-cs from hardware

[Frank Li]

On Thu, Aug 28, 2025 at 11:14:47AM +0100, James Clark wrote:
> Add query_hw_for_num_cs in devtype to avoid directly checking compatible
> string "fsl,imx93-spi".
>
> No functionality change.
>
> Signed-off-by: James Clark <james.clark@linaro.org>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
>  drivers/spi/spi-fsl-lpspi.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
> index ea25e8dab0a4..ce347cdbb009 100644
> --- a/drivers/spi/spi-fsl-lpspi.c
> +++ b/drivers/spi/spi-fsl-lpspi.c
> @@ -87,6 +87,7 @@
>
>  struct fsl_lpspi_devtype_data {
>  	u8 prescale_max : 3; /* 0 == no limit */
> +	bool query_hw_for_num_cs : 1;
>  };
>
>  struct lpspi_config {
> @@ -137,6 +138,7 @@ struct fsl_lpspi_data {
>   */
>  static const struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
>  	.prescale_max = 1,
> +	.query_hw_for_num_cs = true,
>  };
>
>  static const struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
> @@ -932,7 +934,7 @@ static int fsl_lpspi_probe(struct platform_device *pdev)
>  	fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
>  	if (of_property_read_u32((&pdev->dev)->of_node, "num-cs",
>  				 &num_cs)) {
> -		if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx93-spi"))
> +		if (devtype_data->query_hw_for_num_cs)
>  			num_cs = ((temp >> 16) & 0xf);
>  		else
>  			num_cs = 1;
>
> --
> 2.34.1
>

Re: [PATCH v2 9/9] spi: spi-fsl-lpspi: Add compatible for S32G

[Frank Li]

On Thu, Aug 28, 2025 at 11:14:48AM +0100, James Clark wrote:
> From: Larisa Grigore <larisa.grigore@nxp.com>
>
> S32G doesn't have the max prescale erratum (default) and it can query
> the max number of CS from hardware, so add those settings.
>
> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com>
> Signed-off-by: James Clark <james.clark@linaro.org>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/spi/spi-fsl-lpspi.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
> index ce347cdbb009..431439d4cdda 100644
> --- a/drivers/spi/spi-fsl-lpspi.c
> +++ b/drivers/spi/spi-fsl-lpspi.c
> @@ -145,9 +145,14 @@ static const struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
>  	/* All defaults */
>  };
>
> +static const struct fsl_lpspi_devtype_data s32g_lpspi_devtype_data = {
> +	.query_hw_for_num_cs = true,
> +};
> +
>  static const struct of_device_id fsl_lpspi_dt_ids[] = {
>  	{ .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
>  	{ .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
> +	{ .compatible = "nxp,s32g2-lpspi", .data = &s32g_lpspi_devtype_data,},
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
>
> --
> 2.34.1
>

Re: [PATCH v2 1/9] spi: spi-fsl-lpspi: Fix transmissions when using CONT

[Mark Brown]

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On Thu, Aug 28, 2025 at 11:14:40AM +0100, James Clark wrote:
> From: Larisa Grigore <larisa.grigore@nxp.com>
> 
> Commit 6a130448498c ("spi: lpspi: Fix wrong transmission when don't use
> CONT") breaks transmissions when CONT is used. The TDIE interrupt should
> not be disabled in all cases. If CONT is used and the TX transfer is not
> yet completed yet, but the interrupt handler is called because there are
> characters to be received, TDIE is replaced with FCIE. When the transfer
> is finally completed, SR_TDF is set but the interrupt handler isn't
> called again.

Frank, you've reviewed the whole series except for this patch - is there
some issue with it?

[-- Attachment #2: signature.asc --]
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Re: [PATCH v2 1/9] spi: spi-fsl-lpspi: Fix transmissions when using CONT

[Frank Li]

On Fri, Aug 29, 2025 at 01:38:15PM +0200, Mark Brown wrote:
> On Thu, Aug 28, 2025 at 11:14:40AM +0100, James Clark wrote:
> > From: Larisa Grigore <larisa.grigore@nxp.com>
> >
> > Commit 6a130448498c ("spi: lpspi: Fix wrong transmission when don't use
> > CONT") breaks transmissions when CONT is used. The TDIE interrupt should
> > not be disabled in all cases. If CONT is used and the TX transfer is not
> > yet completed yet, but the interrupt handler is called because there are
> > characters to be received, TDIE is replaced with FCIE. When the transfer
> > is finally completed, SR_TDF is set but the interrupt handler isn't
> > called again.
>
> Frank, you've reviewed the whole series except for this patch - is there
> some issue with it?

I need read spec and code to understand code logic. It should be correct.

Reviewed-by: Frank Li <Frank.Li@nxp.com>

Re: [PATCH v2 5/9] dt-bindings: lpspi: Document support for S32G

[Rob Herring (Arm)]

On Thu, 28 Aug 2025 11:14:44 +0100, James Clark wrote:
> From: Larisa Grigore <larisa.grigore@nxp.com>
> 
> Add compatible strings 'nxp,s32g2-lpspi' and 'nxp,s32g3-lpspi' for S32G2
> and S32G3. Require nxp,s32g3-lpspi to fallback to nxp,s32g2-lpspi since
> they are currently compatible.
> 
> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: James Clark <james.clark@linaro.org>
> ---
>  Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v2 0/9] spi: spi-fsl-lpspi: Generic fixes and support for S32G devices

[Mark Brown]

On Thu, 28 Aug 2025 11:14:39 +0100, James Clark wrote:
> Various fixes for LPSI along with some refactorings. None of the fixes
> are strictly related to S32G, however these changes all originate from
> the work to support S32G devices. The only commits that are strictly
> related are for the new s32g2 and s32g3 compatible strings.
> 
> 

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/9] spi: spi-fsl-lpspi: Fix transmissions when using CONT
      commit: 782a7c73078e1301c0c427f21c06377d77dfa541
[2/9] spi: spi-fsl-lpspi: Set correct chip-select polarity bit
      commit: cbe33705864ba2697a2939de715b81538cf32430
[3/9] spi: spi-fsl-lpspi: Reset FIFO and disable module on transfer abort
      commit: e811b088a3641861fc9d2b2b840efc61a0f1907d
[4/9] spi: spi-fsl-lpspi: Clear status register after disabling the module
      commit: dedf9c93dece441e9a0a4836458bc93677008ddd
[5/9] dt-bindings: lpspi: Document support for S32G
      commit: b663fd4532699cc24f5d1094f3859198ee1ed4b6
[6/9] spi: spi-fsl-lpspi: Constify devtype datas
      commit: fb4273faa4d0eeca8cb7265531d48eb084bcceea
[7/9] spi: spi-fsl-lpspi: Treat prescale_max == 0 as no erratum
      commit: 9bbfb1ec959ce95f91cfab544f705e5257be3be1
[8/9] spi: spi-fsl-lpspi: Parameterize reading num-cs from hardware
      commit: 41c91c2eed83cb93781078108077b7e34f867fc2
[9/9] spi: spi-fsl-lpspi: Add compatible for S32G
      commit: 431f6c88cb5d2d62d579d4d78f5c1a2583465ffb

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark