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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-3381cff2f63sm10262891fa.48.2025.09.06.14.34.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Sep 2025 14:34:27 -0700 (PDT) Date: Sun, 7 Sep 2025 00:34:24 +0300 From: Dmitry Baryshkov To: Sebastian Reichel Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Frank Wang , Zhang Yubing , Andy Yan , Maud Spierings , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC 1/2] dt-bindings: phy: rockchip-usbdp: add improved ports scheme Message-ID: References: <20250904-rock5b-dp-alt-mode-v1-0-23df726b31ce@collabora.com> <20250904-rock5b-dp-alt-mode-v1-1-23df726b31ce@collabora.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: 5SPHw4xABBzQ7p_WpuzVcVCZVzxssuBT X-Proofpoint-GUID: 5SPHw4xABBzQ7p_WpuzVcVCZVzxssuBT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAxOCBTYWx0ZWRfX2znAFF+zUpzU uT3vnJhHxkxl7XHXBWbmJjsq9IRRtvXAJ4QNOu8yCDz+Jm0JrvE5IEpLT48KBpm/mPPAK9cKhwi OI0MyjZnuwOrGpv7Otx/XOS1IRGaq6WrBjHjp3jVkZ5b/Ie0w46OlBK2cUBPARpdwFcUGPdH1p6 QU7LePc8j45PcCM+Xh0Le/W90G2TZUWJsWemRVJ7QFqLTgjP7fFsHDUXP7ucqYq5IsobtboKgZ5 1yA8/PBL5HlyjaeD1XlDHxgrUCDz9KsgrCn8Fau6FdrHKBi0TDCLFaX8Y1oYGsuVQuowk2xjztk BQnhReqc0lkWZzz8Uuw/DuOoKjlYF2xBB0A+XxnHUuaMLFclz50jqWlZVyzBdaXNPiYAgwUdKTd V8i4EznB X-Authority-Analysis: v=2.4 cv=G4kcE8k5 c=1 sm=1 tr=0 ts=68bca8e6 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=yJojWOMRYYMA:10 a=JfrnYn6hAAAA:8 a=QX4gbG5DAAAA:8 a=cojAzSgMqaLAs1qlVxgA:9 a=CjuIK1q_8ugA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=1CNFftbPRP8L7MoqJWF3:22 a=AbAUZ8qAyYyZVLSsDulk:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-06_08,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 bulkscore=0 suspectscore=0 clxscore=1015 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060018 On Sat, Sep 06, 2025 at 10:42:22PM +0200, Sebastian Reichel wrote: > Hi, > > On Sat, Sep 06, 2025 at 10:24:54PM +0300, Dmitry Baryshkov wrote: > > On Thu, Sep 04, 2025 at 08:26:02PM +0200, Sebastian Reichel wrote: > > > Currently the Rockchip USBDP PHY as a very simply port scheme: It just > > > offers a single port, which is supposed to point towards the connector. > > > Usually with 2 endpoints, one for the USB-C superspeed port and one for > > > the USB-C SBU port. > > > > > > This scheme is not good enough to properly handle DP AltMode, so add > > > a new scheme, which has separate ports for everything. This has been > > > modelled after the Qualcomm QMP USB4-USB3-DP PHY controller binding > > > with a slight difference that there is an additional port for the > > > USB-C SBU port as the Rockchip USB-DP PHY also contains the mux. > > > > > > Signed-off-by: Sebastian Reichel > > > --- > > > .../bindings/phy/phy-rockchip-usbdp.yaml | 23 ++++++++++++++++++++++ > > > 1 file changed, 23 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > > > index 8b7059d5b1826fdec5170cf78d6e27f2bd6766bb..f728acf057e4046a4d254ee687af3451f17bcd01 100644 > > > --- a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > > > +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > > > @@ -114,6 +114,29 @@ properties: > > > A port node to link the PHY to a TypeC controller for the purpose of > > > handling orientation switching. > > > > > > + ports: > > > + $ref: /schemas/graph.yaml#/properties/ports > > > + properties: > > > + port@0: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: > > > + Output endpoint of the PHY for USB (or DP when configured into 4 lane > > > + mode), which should point to the superspeed port of a USB connector. > > > > What abourt USB+DP mode, where each one gets 2 lanes? > > Right, I guess we would need one port more and have one port for > lane 0 + 1 and one port for 1 + 2. For USB-C both ports are > connected to the USB-C superspeed port. For DP 4-lane mode the > same is done for the input port of the connector. Last but not > least for 2 lanes USB + 2 lanes DP, one port can be connected > to the USB connector and one port can be connected to the DP > connector. Hmm. I'm not sure what do you mean here. Basically, it should be: - Normal USB-C case with DP AltMode: + port@0 routed to connector's port@1 (through mux or retimer if any) + port@4 routed to connector's port@2 (through mux or retimer if any) - Actual DP or mini-DP connector: + port@0 routed to connector's sole port (most likely direcrly) + port@4 most likely unconnected (at least for now, dp-connector doesn't have AUX lines described) - Weird mode of having both USB-A or -C and actual DisplayPort + port@0 should get two endpoints, each having data-lines properties, one endpoint being connected to the USB port, another endpoint being connected to DP connector. + port@4 unconnected (yep, we should extend DP properties, maybe I'll send a patch) I'd say, the first two options are the most important ones. Unless you have actual hardware that uses the USB + separate DP, I'd say, we can ignore that part. > > > > + port@1: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: Incoming endpoint from the USB controller > > > + > > > + port@2: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: Incoming endpoint from the DisplayPort controller > > > + > > > + port@3: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: > > > + Output endpoint of the PHY for DP, which should either point to the > > > + SBU port of a USB-C connector or a DisplayPort connector input port. > > > > I would suggest describing this port as 'DisplayPort AUX signals to be > > connected to the SBU port of a USB-C connector (maybe through the > > additinal mux, switch or retimer)'. It should not be confused with the > > actual DisplayPort signals (as those go through the port@0). > > > > In the Qualcomm world we currently do not describe this link from the > > PHY to the gpio-mux or retimer, but I think we will have to do that > > soon. > > It does looks like no upstream platform does a proper description of > USB-C setups :( > > Thanks for having a look, > > -- Sebastian > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip -- With best wishes Dmitry