From: Andrea Parri <parri.andrea@gmail.com>
To: Xu Lu <luxu.kernel@bytedance.com>
Cc: Guo Ren <guoren@kernel.org>,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, ajones@ventanamicro.com,
brs@rivosinc.com, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
apw@canonical.com, joe@perches.com
Subject: Re: [External] Re: [PATCH v2 0/4] riscv: Add Zalasr ISA extension support
Date: Fri, 19 Sep 2025 09:45:11 +0200 [thread overview]
Message-ID: <aM0KBwkdPFD69oui@andrea> (raw)
In-Reply-To: <CAPYmKFt=5=t_nxY4FadG0_vSgAu1tXyO15OCvo5x6QorqM+BAw@mail.gmail.com>
> The existing implementation of spin_unlock, when followed by
> spin_lock, is equal to 'FENCE rw, rw' for operations before
This is not true without Zacas, that is, when using LR/SC: write-to-read
remains unordered in that case.
Andrea
next prev parent reply other threads:[~2025-09-19 7:45 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-02 4:24 [PATCH v2 0/4] riscv: Add Zalasr ISA extension support Xu Lu
2025-09-02 4:24 ` [PATCH v2 1/4] riscv: add ISA extension parsing for Zalasr Xu Lu
2025-09-02 4:24 ` [PATCH v2 2/4] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
2025-09-02 19:46 ` Conor Dooley
2025-09-02 4:24 ` [PATCH v2 3/4] riscv: Instroduce Zalasr instructions Xu Lu
2025-09-02 4:24 ` [PATCH v2 4/4] riscv: Use Zalasr for smp_load_acquire/smp_store_release Xu Lu
2025-09-03 1:06 ` kernel test robot
2025-09-02 16:59 ` [PATCH v2 0/4] riscv: Add Zalasr ISA extension support Andrea Parri
2025-09-03 11:41 ` [External] " Xu Lu
2025-09-17 4:01 ` Guo Ren
2025-09-17 4:57 ` Guo Ren
2025-09-18 16:48 ` Guo Ren
2025-09-18 21:24 ` Andrea Parri
2025-09-20 5:59 ` Guo Ren
2025-09-19 3:18 ` [External] " Xu Lu
2025-09-19 7:45 ` Andrea Parri [this message]
2025-09-19 8:22 ` Xu Lu
2025-09-20 6:04 ` Guo Ren
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