[PATCH 0/7] RISC-V: Add support for Tenstorrent Blackhole SoC

[PATCH 0/7] RISC-V: Add support for Tenstorrent Blackhole SoC

[Drew Fustini]

Enable support for the Tenstorrent Blackhole A0 SoC in the Blackhole
P100 and P150 PCIe cards [1]. The Blackhole SoC contains four RISC-V
CPU tiles consisting of 4x SiFive X280 cores. Each tile is capable of
running an instance of Linux.

There is a public Linux-on-Blackhole project [2] that enables users to
boot Linux on Blackhole PCIe cards. A boot script on the PCIe host
loads the kernel image and the rootfs into DDR memory and then takes
the X280 cores out of reset.

All the low-level SoC initialization is handled by firmware [3] running
on a separate management core in the Blackhole SoC. Linux on the X280
cores does not need to deal with any clocks, reset, etc. The management
core firmware also controls the PCIe EP functionality. The tt-kmd Linux
kernel driver [4] on the PCIe host allows the host to interact with the
DDR memory on the Blackhole PCIe card along with other tiles in the SoC
accessible from the NoC [5].

There is a virtual UART implemented in OpenSBI [6] that allows a console
program on the PCIe host to communicate through shared memory with Linux
running on the Blackhole. This does require CONFIG_HVC_RISCV_SBI which
is currently hidden behind CONFIG_NONPORTABLE. I would like Blackhole to
work with defconfig, so I'm looking into possible ways of solving the
issue that caused HVC SBI to be guarded by NONPORTABLE [7].

The public Linux-on-Blackhole project does also make use of virtio to
provide networking and storage. However, this relies on changes in our
downstream kernel branch [8], so I've removed those dt nodes from this
upstream dts series. We hope to eventually leverage the virtio-msg spec
to upstream the virtio functionality, too.

I have also dropped the bootargs from this series. Instead, I will add
the ability to fixup the dtb to the boot script on the host [9]. It does
need 'console=hvc0' to ensure the full boot output appears in the
console program on the host. I also dropped the pmem node from this
series as I don't see any upstream users of pmem. I have been using pmem
for the rootfs, so I'll update the boot script to add the pmem node and
amend 'root=/dev/pmem0' in bootargs.

TL;DR:
The goal for upstreaming this rather minimal device tree in this series
is to make it possible to boot mainline kernel builds. I attended the
recent KernelCI workshop, and there are not currently many RISC-V boards
doing boot tests. I think the Blackhole cards could help improve the
situation once Blackhole is able to boot important trees like mainline
and next. The HVC SBI console is sufficient for boot testing.

[1] https://tenstorrent.com/hardware/blackhole
[2] https://github.com/tenstorrent/tt-bh-linux
[3] https://github.com/tenstorrent/tt-zephyr-platforms
[4] https://github.com/tenstorrent/tt-kmd
[5] https://github.com/tenstorrent/tt-isa-documentation/blob/main/BlackholeA0/
[6] https://github.com/tenstorrent/opensbi/
[7] https://lore.kernel.org/all/20240214153429.16484-2-palmer@rivosinc.com/
[8] https://github.com/tenstorrent/linux/
[9] https://github.com/tenstorrent/tt-bh-linux/blob/dfustini/kernelci/boot.py

Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
Drew Fustini (7):
      dt-bindings: vendor-prefixes: Add Tenstorrent AI ULC
      dt-bindings: riscv: Add Tenstorrent Blackhole compatible
      dt-bindings: riscv: cpus: Add SiFive X280 compatible
      dt-bindings: timers: Add Tenstorrent Blackhole compatible
      dt-bindings: interrupt-controller: Add Tenstorrent Blackhole compatible
      riscv: dts: Add Tenstorrent Blackhole A0 SoC PCIe cards
      riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs

 .../interrupt-controller/sifive,plic-1.0.0.yaml    |   1 +
 Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
 .../devicetree/bindings/riscv/tenstorrent.yaml     |  28 ++++++
 .../devicetree/bindings/timer/sifive,clint.yaml    |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 MAINTAINERS                                        |   9 ++
 arch/riscv/Kconfig.socs                            |   8 ++
 arch/riscv/boot/dts/Makefile                       |   1 +
 arch/riscv/boot/dts/tenstorrent/Makefile           |   2 +
 .../boot/dts/tenstorrent/blackhole-a0-card.dts     |  14 +++
 arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi  | 112 +++++++++++++++++++++
 11 files changed, 179 insertions(+)
---
base-commit: 76eeb9b8de9880ca38696b2fb56ac45ac0a25c6c
change-id: 20250912-tt-bh-dts-d7bcc507a556

Best regards,
-- 
Drew Fustini <dfustini@tenstorrent.com>

[PATCH 1/7] dt-bindings: vendor-prefixes: Add Tenstorrent AI ULC

[Drew Fustini]

From: Drew Fustini <dfustini@tenstorrent.com>

Document vendor prefix for Tenstorrent in DT bindings.

Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 9ec8947dfcad2fa53b2dca2ca06a63710771a600..8bbc0ebdfb9eb5864f2797251a8d144e2eea9a92 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1547,6 +1547,8 @@ patternProperties:
     description: Teltonika Networks
   "^tempo,.*":
     description: Tempo Semiconductor
+  "^tenstorrent,.*":
+    description: Tenstorrent AI ULC
   "^terasic,.*":
     description: Terasic Inc.
   "^tesla,.*":

-- 
2.34.1

[PATCH 2/7] dt-bindings: riscv: Add Tenstorrent Blackhole compatible

[Drew Fustini]

From: Drew Fustini <dfustini@tenstorrent.com>

Add compatibles for the Tenstorrent Blackhole A0 SoC PCIe card.

Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
 .../devicetree/bindings/riscv/tenstorrent.yaml     | 28 ++++++++++++++++++++++
 MAINTAINERS                                        |  8 +++++++
 2 files changed, 36 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/tenstorrent.yaml b/Documentation/devicetree/bindings/riscv/tenstorrent.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..877da1b0214f6730713369f82a1fdcc44c4ea562
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/tenstorrent.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/tenstorrent.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tenstorrent SoC-based boards
+
+maintainers:
+  - Drew Fustini <dfustini@tenstorrent.com>
+  - Joel Stanley <jms@tenstorrent.com>
+
+description:
+  Tenstorrent SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Tenstorrent Blackhole A0 PCIe card
+        items:
+          - const: tenstorrent,blackhole-a0-card
+          - const: tenstorrent,blackhole-a0
+
+additionalProperties: true
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index cd7ff55b5d321752ac44c91d2d7e74de28e08960..f2cb2aae8d66d21bf5c13b16b3b1d8fdc98b9462 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21741,6 +21741,14 @@ F:	arch/riscv/boot/dts/spacemit/
 N:	spacemit
 K:	spacemit
 
+RISC-V TENSTORRENT SoC SUPPORT
+M:	Drew Fustini <dfustini@tenstorrent.com>
+M:	Joel Stanley <jms@tenstorrent.com>
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+T:	git https://github.com/tenstorrent/linux.git
+F:	Documentation/devicetree/bindings/riscv/tenstorrent.yaml
+
 RISC-V THEAD SoC SUPPORT
 M:	Drew Fustini <fustini@kernel.org>
 M:	Guo Ren <guoren@kernel.org>

-- 
2.34.1

[PATCH 3/7] dt-bindings: riscv: cpus: Add SiFive X280 compatible

[Drew Fustini]

From: Drew Fustini <dfustini@tenstorrent.com>

Document compatible for the SiFive X280 RISC-V core.

Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 1a0cf0702a45d2df38c48f50d66b3d2ac3715da5..bbc3886282dc5e8c53e54c0acd91608b443f590f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -69,6 +69,7 @@ properties:
           - enum:
               - sifive,e51
               - sifive,u54-mc
+              - sifive,x280
           - const: sifive,rocket0
           - const: riscv
       - const: riscv    # Simulator only

-- 
2.34.1

[PATCH 4/7] dt-bindings: timers: Add Tenstorrent Blackhole compatible

[Drew Fustini]

From: Drew Fustini <dfustini@tenstorrent.com>

Document clint compatible for the Tenstorrent Blackhole A0 SoC.

Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index d85a1a088b35dabc0aa202475b926302705c4cf1..198146c59de0c95a2ffa052c8d4d7aa3f91f8e92 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -36,6 +36,7 @@ properties:
               - starfive,jh7100-clint   # StarFive JH7100
               - starfive,jh7110-clint   # StarFive JH7110
               - starfive,jh8100-clint   # StarFive JH8100
+              - tenstorrent,blackhole-a0-clint # Tenstorrent Blackhole
           - const: sifive,clint0        # SiFive CLINT v0 IP block
       - items:
           - {}

-- 
2.34.1

[PATCH 5/7] dt-bindings: interrupt-controller: Add Tenstorrent Blackhole compatible

[Drew Fustini]

From: Drew Fustini <dfustini@tenstorrent.com>

Document compatible for the PLIC in the Tenstorrent Blackhole A0 SoC.

Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
 .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml      | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 5b827bc243011cda1fd45d739d34eca95c6e1ee2..c960a9ec17e9fceb0b754c21162e8730b12120fb 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -63,6 +63,7 @@ properties:
               - spacemit,k1-plic
               - starfive,jh7100-plic
               - starfive,jh7110-plic
+              - tenstorrent,blackhole-a0-plic
           - const: sifive,plic-1.0.0
       - items:
           - enum:

-- 
2.34.1

[PATCH 6/7] riscv: dts: Add Tenstorrent Blackhole A0 SoC PCIe cards

[Drew Fustini]

From: Drew Fustini <dfustini@tenstorrent.com>

Add device tree source describing the Tenstorrent Blackhole A0 SoC and
the Blackhole P100 and P150 PCIe cards. There are no differences between
the P100 and P150 cards from the perspective of an OS kernel like Linux
running on the X280 cores.

Link: https://github.com/tenstorrent/tt-isa-documentation/blob/main/BlackholeA0/
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
 MAINTAINERS                                        |   1 +
 arch/riscv/boot/dts/Makefile                       |   1 +
 arch/riscv/boot/dts/tenstorrent/Makefile           |   2 +
 .../boot/dts/tenstorrent/blackhole-a0-card.dts     |  14 +++
 arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi  | 112 +++++++++++++++++++++
 5 files changed, 130 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index f2cb2aae8d66d21bf5c13b16b3b1d8fdc98b9462..20605d7530a6d19e928709647ea91a9cf7913ee7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21748,6 +21748,7 @@ L:	linux-riscv@lists.infradead.org
 S:	Maintained
 T:	git https://github.com/tenstorrent/linux.git
 F:	Documentation/devicetree/bindings/riscv/tenstorrent.yaml
+F:	arch/riscv/boot/dts/tenstorrent/
 
 RISC-V THEAD SoC SUPPORT
 M:	Drew Fustini <fustini@kernel.org>
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 3b99e91efa25be2d6ca5bc173342c24a72f87187..0624199867065dbb5eb62d660f950b4aa3a7abd7 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -8,4 +8,5 @@ subdir-y += sifive
 subdir-y += sophgo
 subdir-y += spacemit
 subdir-y += starfive
+subdir-y += tenstorrent
 subdir-y += thead
diff --git a/arch/riscv/boot/dts/tenstorrent/Makefile b/arch/riscv/boot/dts/tenstorrent/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..009510bea6c8e558bda70850a7f8490b23bffdea
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_TENSTORRENT) += blackhole-a0-card.dtb
diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
new file mode 100644
index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/dts-v1/;
+
+#include "blackhole-a0.dtsi"
+
+/ {
+	model = "Tenstorrent Blackhole A0 SoC PCIe card";
+	compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x4000 0x30000000 0x1 0x00000000>;
+	};
+};
diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..517b6442ff0fe61659069e29318ad3f01bc504e2
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright 2025 Tenstorrent AI ULC
+/dts-v1/;
+
+/ {
+	compatible = "tenstorrent,blackhole-a0";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <50000000>;
+
+		cpu@0 {
+			compatible = "sifive,x280", "sifive,rocket0", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			mmu-type = "riscv,sv57";
+			riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
+					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";
+			riscv,cboz-block-size = <0x40>;
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@1 {
+			compatible = "sifive,x280", "sifive,rocket0", "riscv";
+			device_type = "cpu";
+			reg = <1>;
+			mmu-type = "riscv,sv57";
+			riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
+					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";
+			riscv,cboz-block-size = <0x40>;
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@2 {
+			compatible = "sifive,x280", "sifive,rocket0", "riscv";
+			device_type = "cpu";
+			reg = <2>;
+			mmu-type = "riscv,sv57";
+			riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
+					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";
+			riscv,cboz-block-size = <0x40>;
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@3 {
+			compatible = "sifive,x280", "sifive,rocket0", "riscv";
+			device_type = "cpu";
+			reg = <3>;
+			mmu-type = "riscv,sv57";
+			riscv,isa-base = "rv64i";
+			riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
+					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";
+			riscv,cboz-block-size = <0x40>;
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		clint0: timer@2000000 {
+			compatible = "tenstorrent,blackhole-a0-clint", "sifive,clint0";
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>,
+					      <&cpu1_intc 0x3>, <&cpu1_intc 0x7>,
+					      <&cpu2_intc 0x3>, <&cpu2_intc 0x7>,
+					      <&cpu3_intc 0x3>, <&cpu3_intc 0x7>;
+		};
+
+		plic0: interrupt-controller@c000000 {
+			compatible = "tenstorrent,blackhole-a0-plic", "sifive,plic-1.0.0";
+			reg = <0x0 0x0c000000 0x0 0x04000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			riscv,ndev = <128>;
+		};
+	};
+};

-- 
2.34.1

[PATCH 7/7] riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs

[Drew Fustini]

From: Drew Fustini <dfustini@tenstorrent.com>

Add Kconfig option ARCH_TENSTORRENT to enable support for SoCs like the
Blackhole A0.

Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
 arch/riscv/Kconfig.socs | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 61ceae0aa27a6fa3a91da6a46becfd96da99fd09..ff733a998612d429e7b1e00276eb86290d8331a3 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -57,6 +57,14 @@ config ARCH_SUNXI
 	  This enables support for Allwinner sun20i platform hardware,
 	  including boards based on the D1 and D1s SoCs.
 
+config ARCH_TENSTORRENT
+	bool "Tenstorrent SoCs"
+	help
+	  This enables support for Tenstorrent SoC platforms.
+	  Current support is for Blackhole P100 and P150 PCIe cards.
+	  The Blackhole A0 SoC contains four RISC-V CPU tiles each
+	  consisting of 4x SiFive X280 cores.
+
 config ARCH_THEAD
 	bool "T-HEAD RISC-V SoCs"
 	depends on MMU && !XIP_KERNEL

-- 
2.34.1

Re: [PATCH 6/7] riscv: dts: Add Tenstorrent Blackhole A0 SoC PCIe cards

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1849 bytes --]

On Sat, Sep 13, 2025 at 02:31:05PM -0700, Drew Fustini wrote:
> new file mode 100644
> index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/dts-v1/;
> +
> +#include "blackhole-a0.dtsi"
> +
> +/ {
> +	model = "Tenstorrent Blackhole A0 SoC PCIe card";
> +	compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
> +
> +	memory@0 {
> +		device_type = "memory";
> +		reg = <0x4000 0x30000000 0x1 0x00000000>;

This isn't at address zero as the node address claims.

> +	};
> +};
> diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..517b6442ff0fe61659069e29318ad3f01bc504e2
> --- /dev/null
> +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
> @@ -0,0 +1,112 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +// Copyright 2025 Tenstorrent AI ULC
> +/dts-v1/;
> +
> +/ {
> +	compatible = "tenstorrent,blackhole-a0";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <0x1>;
> +		#size-cells = <0x0>;
> +		timebase-frequency = <50000000>;
> +
> +		cpu@0 {
> +			compatible = "sifive,x280", "sifive,rocket0", "riscv";
> +			device_type = "cpu";
> +			reg = <0>;
> +			mmu-type = "riscv,sv57";

> +			riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";

What's the benefit of retaining this property?

> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
> +					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";
> +			riscv,cboz-block-size = <0x40>;

cboz block size, but no zicboz in your extensions list?

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Re: [PATCH 7/7] riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs

[Conor Dooley]

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On Sat, Sep 13, 2025 at 02:31:06PM -0700, Drew Fustini wrote:
> From: Drew Fustini <dfustini@tenstorrent.com>
> 
> Add Kconfig option ARCH_TENSTORRENT to enable support for SoCs like the
> Blackhole A0.
> 
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
>  arch/riscv/Kconfig.socs | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 61ceae0aa27a6fa3a91da6a46becfd96da99fd09..ff733a998612d429e7b1e00276eb86290d8331a3 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -57,6 +57,14 @@ config ARCH_SUNXI
>  	  This enables support for Allwinner sun20i platform hardware,
>  	  including boards based on the D1 and D1s SoCs.
>  
> +config ARCH_TENSTORRENT
> +	bool "Tenstorrent SoCs"
> +	help
> +	  This enables support for Tenstorrent SoC platforms.
> +	  Current support is for Blackhole P100 and P150 PCIe cards.
> +	  The Blackhole A0 SoC contains four RISC-V CPU tiles each
> +	  consisting of 4x SiFive X280 cores.

Can you add this to defconfig too, so that it gets build by default in
that configuration?

> +
>  config ARCH_THEAD
>  	bool "T-HEAD RISC-V SoCs"
>  	depends on MMU && !XIP_KERNEL
> 
> -- 
> 2.34.1
> 

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Re: [PATCH 6/7] riscv: dts: Add Tenstorrent Blackhole A0 SoC PCIe cards

[Drew Fustini]

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On Mon, Sep 15, 2025 at 05:47:08PM +0100, Conor Dooley wrote:
> On Sat, Sep 13, 2025 at 02:31:05PM -0700, Drew Fustini wrote:
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
> > @@ -0,0 +1,14 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/dts-v1/;
> > +
> > +#include "blackhole-a0.dtsi"
> > +
> > +/ {
> > +	model = "Tenstorrent Blackhole A0 SoC PCIe card";
> > +	compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
> > +
> > +	memory@0 {
> > +		device_type = "memory";
> > +		reg = <0x4000 0x30000000 0x1 0x00000000>;
> 
> This isn't at address zero as the node address claims.

Thanks, I'll fix the unit address.

> 
> > +	};
> > +};
> > diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..517b6442ff0fe61659069e29318ad3f01bc504e2
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
> > @@ -0,0 +1,112 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +// Copyright 2025 Tenstorrent AI ULC
> > +/dts-v1/;
> > +
> > +/ {
> > +	compatible = "tenstorrent,blackhole-a0";
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	cpus {
> > +		#address-cells = <0x1>;
> > +		#size-cells = <0x0>;
> > +		timebase-frequency = <50000000>;
> > +
> > +		cpu@0 {
> > +			compatible = "sifive,x280", "sifive,rocket0", "riscv";
> > +			device_type = "cpu";
> > +			reg = <0>;
> > +			mmu-type = "riscv,sv57";
> 
> > +			riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";
> 
> What's the benefit of retaining this property?

Nothing depends on the legacy isa property so I'll drop it.

> 
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
> > +					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";
> > +			riscv,cboz-block-size = <0x40>;
> 
> cboz block size, but no zicboz in your extensions list?

My mistake, the core does not have CBO so I'll drop this property.

Thanks,
Drew

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Re: [PATCH 7/7] riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs

[Drew Fustini]

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On Mon, Sep 15, 2025 at 05:48:06PM +0100, Conor Dooley wrote:
> On Sat, Sep 13, 2025 at 02:31:06PM -0700, Drew Fustini wrote:
> > From: Drew Fustini <dfustini@tenstorrent.com>
> > 
> > Add Kconfig option ARCH_TENSTORRENT to enable support for SoCs like the
> > Blackhole A0.
> > 
> > Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> > ---
> >  arch/riscv/Kconfig.socs | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 61ceae0aa27a6fa3a91da6a46becfd96da99fd09..ff733a998612d429e7b1e00276eb86290d8331a3 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -57,6 +57,14 @@ config ARCH_SUNXI
> >  	  This enables support for Allwinner sun20i platform hardware,
> >  	  including boards based on the D1 and D1s SoCs.
> >  
> > +config ARCH_TENSTORRENT
> > +	bool "Tenstorrent SoCs"
> > +	help
> > +	  This enables support for Tenstorrent SoC platforms.
> > +	  Current support is for Blackhole P100 and P150 PCIe cards.
> > +	  The Blackhole A0 SoC contains four RISC-V CPU tiles each
> > +	  consisting of 4x SiFive X280 cores.
> 
> Can you add this to defconfig too, so that it gets build by default in
> that configuration?

Sure, will do.

Thanks,
Drew

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Re: [PATCH 1/7] dt-bindings: vendor-prefixes: Add Tenstorrent AI ULC

[Rob Herring (Arm)]

On Sat, 13 Sep 2025 14:31:00 -0700, Drew Fustini wrote:
> From: Drew Fustini <dfustini@tenstorrent.com>
> 
> Document vendor prefix for Tenstorrent in DT bindings.
> 
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 2/7] dt-bindings: riscv: Add Tenstorrent Blackhole compatible

[Rob Herring (Arm)]

On Sat, 13 Sep 2025 14:31:01 -0700, Drew Fustini wrote:
> From: Drew Fustini <dfustini@tenstorrent.com>
> 
> Add compatibles for the Tenstorrent Blackhole A0 SoC PCIe card.
> 
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
>  .../devicetree/bindings/riscv/tenstorrent.yaml     | 28 ++++++++++++++++++++++
>  MAINTAINERS                                        |  8 +++++++
>  2 files changed, 36 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 3/7] dt-bindings: riscv: cpus: Add SiFive X280 compatible

[Rob Herring (Arm)]

On Sat, 13 Sep 2025 14:31:02 -0700, Drew Fustini wrote:
> From: Drew Fustini <dfustini@tenstorrent.com>
> 
> Document compatible for the SiFive X280 RISC-V core.
> 
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 4/7] dt-bindings: timers: Add Tenstorrent Blackhole compatible

[Rob Herring]

On Sat, Sep 13, 2025 at 02:31:03PM -0700, Drew Fustini wrote:
> From: Drew Fustini <dfustini@tenstorrent.com>
> 
> Document clint compatible for the Tenstorrent Blackhole A0 SoC.
> 
> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index d85a1a088b35dabc0aa202475b926302705c4cf1..198146c59de0c95a2ffa052c8d4d7aa3f91f8e92 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -36,6 +36,7 @@ properties:
>                - starfive,jh7100-clint   # StarFive JH7100
>                - starfive,jh7110-clint   # StarFive JH7110
>                - starfive,jh8100-clint   # StarFive JH8100
> +              - tenstorrent,blackhole-a0-clint # Tenstorrent Blackhole

We usually don't put Si versions (A0) in compatible strings unless later 
versions changed in incompatible ways. Perhaps if you already knew that 
B0 was different, then it would be appropriate. Or am I misunderstanding 
what A0 means?

Rob

Re: [PATCH 6/7] riscv: dts: Add Tenstorrent Blackhole A0 SoC PCIe cards

[Ben Dooks]

On 15/09/2025 18:52, Drew Fustini wrote:
> On Mon, Sep 15, 2025 at 05:47:08PM +0100, Conor Dooley wrote:
>> On Sat, Sep 13, 2025 at 02:31:05PM -0700, Drew Fustini wrote:
>>> new file mode 100644
>>> index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
>>> @@ -0,0 +1,14 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/dts-v1/;
>>> +
>>> +#include "blackhole-a0.dtsi"
>>> +
>>> +/ {
>>> +	model = "Tenstorrent Blackhole A0 SoC PCIe card";
>>> +	compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
>>> +
>>> +	memory@0 {
>>> +		device_type = "memory";
>>> +		reg = <0x4000 0x30000000 0x1 0x00000000>;
>>
>> This isn't at address zero as the node address claims.
> 
> Thanks, I'll fix the unit address.

Is it time to just assume any dtc can handle a 64bit number?


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

Re: [PATCH 6/7] riscv: dts: Add Tenstorrent Blackhole A0 SoC PCIe cards

[Drew Fustini]

On Tue, Sep 16, 2025 at 02:56:05PM +0100, Ben Dooks wrote:
> On 15/09/2025 18:52, Drew Fustini wrote:
> > On Mon, Sep 15, 2025 at 05:47:08PM +0100, Conor Dooley wrote:
> > > On Sat, Sep 13, 2025 at 02:31:05PM -0700, Drew Fustini wrote:
> > > > new file mode 100644
> > > > index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
> > > > @@ -0,0 +1,14 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > +/dts-v1/;
> > > > +
> > > > +#include "blackhole-a0.dtsi"
> > > > +
> > > > +/ {
> > > > +	model = "Tenstorrent Blackhole A0 SoC PCIe card";
> > > > +	compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
> > > > +
> > > > +	memory@0 {
> > > > +		device_type = "memory";
> > > > +		reg = <0x4000 0x30000000 0x1 0x00000000>;
> > > 
> > > This isn't at address zero as the node address claims.
> > 
> > Thanks, I'll fix the unit address.
> 
> Is it time to just assume any dtc can handle a 64bit number?

Is it not valid for me to use the 64 bit hex number in the unit address?

I changed it to memory@400030000000 and 'W=1 dtbs_check' did not
complain. Am I doing something wrong?

-------------------------------------------------
$ git diff
diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
index b2b08023643a..7963712b53ea 100644
--- a/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
+++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
@@ -7,7 +7,7 @@ / {
        model = "Tenstorrent Blackhole A0 SoC PCIe card";
        compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";

-       memory@0 {
+       memory@400030000000 {
                device_type = "memory";
                reg = <0x4000 0x30000000 0x1 0x00000000>;
        };


$ make W=1 ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- -j32 dtbs_check
  DTC [C] arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dtb
  DTC [C] arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dtb
  DTC [C] arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dtb
-------------------------------------------------

Thanks,
Drew

Re: [PATCH 4/7] dt-bindings: timers: Add Tenstorrent Blackhole compatible

[Drew Fustini]

On Tue, Sep 16, 2025 at 08:44:00AM -0500, Rob Herring wrote:
> On Sat, Sep 13, 2025 at 02:31:03PM -0700, Drew Fustini wrote:
> > From: Drew Fustini <dfustini@tenstorrent.com>
> > 
> > Document clint compatible for the Tenstorrent Blackhole A0 SoC.
> > 
> > Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
> > ---
> >  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > index d85a1a088b35dabc0aa202475b926302705c4cf1..198146c59de0c95a2ffa052c8d4d7aa3f91f8e92 100644
> > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > @@ -36,6 +36,7 @@ properties:
> >                - starfive,jh7100-clint   # StarFive JH7100
> >                - starfive,jh7110-clint   # StarFive JH7110
> >                - starfive,jh8100-clint   # StarFive JH8100
> > +              - tenstorrent,blackhole-a0-clint # Tenstorrent Blackhole
> 
> We usually don't put Si versions (A0) in compatible strings unless later 
> versions changed in incompatible ways. Perhaps if you already knew that 
> B0 was different, then it would be appropriate. Or am I misunderstanding 
> what A0 means?
> 
> Rob

Okay, thanks for explaining. A0 is the silicon revision, and it is
currently the only version that exists. I was just trying to be as
specific as possible. I'm okay with dropping '-a0'.

Should I change the plic compatible to 'tenstorrent,blackhole-plic' too?

I see you gave a Rb for riscv/tenstorrent.yaml but that does have
'tenstorrent,blackhole-a0-card' and 'tenstorrent,blackhole-a0'. Should I
drop '-a0' from those too or leave as-is?

Thanks,
Drew

Re: [PATCH 6/7] riscv: dts: Add Tenstorrent Blackhole A0 SoC PCIe cards

[Ben Dooks]

On 16/09/2025 18:27, Drew Fustini wrote:
> On Tue, Sep 16, 2025 at 02:56:05PM +0100, Ben Dooks wrote:
>> On 15/09/2025 18:52, Drew Fustini wrote:
>>> On Mon, Sep 15, 2025 at 05:47:08PM +0100, Conor Dooley wrote:
>>>> On Sat, Sep 13, 2025 at 02:31:05PM -0700, Drew Fustini wrote:
>>>>> new file mode 100644
>>>>> index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
>>>>> --- /dev/null
>>>>> +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
>>>>> @@ -0,0 +1,14 @@
>>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>>> +/dts-v1/;
>>>>> +
>>>>> +#include "blackhole-a0.dtsi"
>>>>> +
>>>>> +/ {
>>>>> +	model = "Tenstorrent Blackhole A0 SoC PCIe card";
>>>>> +	compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
>>>>> +
>>>>> +	memory@0 {
>>>>> +		device_type = "memory";
>>>>> +		reg = <0x4000 0x30000000 0x1 0x00000000>;
>>>>
>>>> This isn't at address zero as the node address claims.
>>>
>>> Thanks, I'll fix the unit address.
>>
>> Is it time to just assume any dtc can handle a 64bit number?
> 
> Is it not valid for me to use the 64 bit hex number in the unit address?
> 
>

No, the reg = < > contents. It is a right pain to read split 32bit
numbers and I thought dtc had been updated to allow 64bit now?



-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html