From: Will Deacon <will@kernel.org>
To: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Cc: "Liang, Kan" <kan.liang@linux.intel.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Conor Dooley <conor+dt@kernel.org>,
Douglas Anderson <dianders@chromium.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Ian Rogers <irogers@google.com>, Ingo Molnar <mingo@redhat.com>,
James Clark <james.clark@linaro.org>,
Jiri Olsa <jolsa@kernel.org>,
John Garry <john.g.garry@oracle.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Leo Yan <leo.yan@linux.dev>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Mike Leach <mike.leach@linaro.org>,
Namhyung Kim <namhyung@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Peter Zijlstra <peterz@infradead.org>,
Rob Herring <robh@kernel.org>,
Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Marc Zyngier <maz@kernel.org>
Subject: Re: [PATCH v3 3/6] arm64: cputype: Add Cortex-A720AE definitions
Date: Tue, 16 Sep 2025 09:53:00 +0100 [thread overview]
Message-ID: <aMklbKwro2bSX76t@willie-the-truck> (raw)
In-Reply-To: <87plbri0k3.wl-kuninori.morimoto.gx@renesas.com>
On Tue, Sep 16, 2025 at 02:38:36AM +0000, Kuninori Morimoto wrote:
> Add cputype definitions for Cortex-A720AE.
> This patch is assuming A720AE feature is same as A720.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> ---
> arch/arm64/include/asm/cputype.h | 2 ++
> arch/arm64/kernel/cpu_errata.c | 1 +
> arch/arm64/kernel/proton-pack.c | 1 +
> tools/arch/arm64/include/asm/cputype.h | 2 ++
> tools/perf/util/arm-spe.c | 1 +
> 5 files changed, 7 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index 661735616787e..b10eba7f52476 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -96,6 +96,7 @@
> #define ARM_CPU_PART_NEOVERSE_V3 0xD84
> #define ARM_CPU_PART_CORTEX_X925 0xD85
> #define ARM_CPU_PART_CORTEX_A725 0xD87
> +#define ARM_CPU_PART_CORTEX_A720AE 0xD89
> #define ARM_CPU_PART_NEOVERSE_N3 0xD8E
>
> #define APM_CPU_PART_XGENE 0x000
> @@ -185,6 +186,7 @@
> #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
> #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
> #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
> +#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
> #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
> #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
> #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 59d723c9ab8f5..7ff6b49beaaff 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -531,6 +531,7 @@ static const struct midr_range erratum_spec_ssbs_list[] = {
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
> diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c
> index edf1783ffc817..f9a32dfde0067 100644
> --- a/arch/arm64/kernel/proton-pack.c
> +++ b/arch/arm64/kernel/proton-pack.c
> @@ -884,6 +884,7 @@ static u8 spectre_bhb_loop_affected(void)
> static const struct midr_range spectre_bhb_k38_list[] = {
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
This needs an Ack from somebody at Arm who can confirm that (a) k38 is
correct for A720AE and (b) that all versions of the CPU are affected.
> diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h
> index 139d5e87dc959..0192dc7ec9ca9 100644
> --- a/tools/arch/arm64/include/asm/cputype.h
> +++ b/tools/arch/arm64/include/asm/cputype.h
> @@ -96,6 +96,7 @@
> #define ARM_CPU_PART_NEOVERSE_V3 0xD84
> #define ARM_CPU_PART_CORTEX_X925 0xD85
> #define ARM_CPU_PART_CORTEX_A725 0xD87
> +#define ARM_CPU_PART_CORTEX_A720AE 0xD89
> #define ARM_CPU_PART_NEOVERSE_N3 0xD8E
>
> #define APM_CPU_PART_XGENE 0x000
> @@ -185,6 +186,7 @@
> #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
> #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
> #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
> +#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
> #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
> #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
> #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
> diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
> index 8942fa598a84f..bda6f3554f7e6 100644
> --- a/tools/perf/util/arm-spe.c
> +++ b/tools/perf/util/arm-spe.c
> @@ -555,6 +555,7 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq,
>
> static const struct midr_range common_ds_encoding_cpus[] = {
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
Please post tools/ patches separately as they are merged independently
of the kernel changes.
Will
next prev parent reply other threads:[~2025-09-16 8:53 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-16 2:37 [PATCH v3 0/6] arm64: add R8A78000 support Kuninori Morimoto
2025-09-16 2:38 ` [PATCH v3 1/6] dt-bindings: soc: renesas: Document R-Car X5H Ironhide Kuninori Morimoto
2025-09-16 10:18 ` Geert Uytterhoeven
2025-09-16 2:38 ` [PATCH v3 2/6] soc: renesas: Identify R-Car X5H Kuninori Morimoto
2025-09-16 10:19 ` Geert Uytterhoeven
2025-09-16 2:38 ` [PATCH v3 3/6] arm64: cputype: Add Cortex-A720AE definitions Kuninori Morimoto
2025-09-16 8:53 ` Will Deacon [this message]
2025-09-16 11:10 ` Mark Rutland
2025-09-16 2:38 ` [PATCH v3 4/6] dt-bindings: arm: cpus: Add Cortex-A720AE Kuninori Morimoto
2025-09-16 10:21 ` Geert Uytterhoeven
2025-09-16 2:38 ` [PATCH v3 5/6] arm64: dts: renesas: Add R8A78000 X5H DTs Kuninori Morimoto
2025-09-16 10:45 ` Marc Zyngier
2025-09-17 4:08 ` Kuninori Morimoto
2025-09-17 7:53 ` Marc Zyngier
2025-09-17 17:52 ` Wolfram Sang
2025-09-18 0:19 ` Kuninori Morimoto
2025-09-16 2:38 ` [PATCH v3 6/6] arm64: dts: renesas: R8A78000: Add initial Ironhide support Kuninori Morimoto
2025-09-17 15:00 ` [PATCH v3 0/6] arm64: add R8A78000 support Rob Herring (Arm)
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