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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?R5bc6GiTf7Xcyb6e7EFUxaHyurKPPGHqezXGzYZSsWrmCdlE4Tf72ch4OYoZ?= =?us-ascii?Q?PSD2BC9mvJeCgl0oQg9gRN6MiJ0Ayihf+wQWO8TXvhcHaLEMxi0fe2+w4aQy?= =?us-ascii?Q?ALumrJYVCUoP9aPZPFJKP7NBGTfvBZJedvCFNwdlhZsvECiBwjF8SMnUweO7?= =?us-ascii?Q?ejuhukQ+cAgF5zRbucZNkZLIYJ1uOMVTHWctkB7ykdDAX5a8Gubxei/ZQCdB?= =?us-ascii?Q?jmtTaFqGmIt7tjXHdOwRFErWsXII7/S38C+HMLPX1356DVicphr5jPpcS4Fy?= =?us-ascii?Q?GdsQvWz2jU/iIgMbiJquZUNeTc86fDVIHhLRJCrsaCjgdOeC1fUUcZ3gAKSH?= =?us-ascii?Q?+2idHI7Vjc6oxA+lEpFbAHnKIToXKrrOpoh3sODOhmFJyoMPfTh3tM24zWQ8?= =?us-ascii?Q?r2dE0FRNa07XT+AAepsDCvQ69CH/twhdrIzEj+YRpgGCW/qHaWp83FUypwL6?= =?us-ascii?Q?IKy8fypni8+UZ13avF0VdtgkKLLmKkvqiDb7fglxgBFpaeXufZVtRTrp8HZF?= =?us-ascii?Q?vihbcB+ZQbgzVC7wIVA3STWxlV5Vf/7BzShh6rEN5M1VvwJu9MV0UMsOU9ej?= =?us-ascii?Q?7ETozVNgJ0Wf6MPLOUqp5q5AvZaUJ/O2UY4esDa6IR2Nx/fqr6SK7RwbEMj7?= =?us-ascii?Q?s/Tfx42VfPR/bvMre4f40H+4Eoh6X8OQaA/zdskaXiU/nfqM1X4OHACwoQj/?= =?us-ascii?Q?8x70nGoNcEaIyadVy7nRni7BJsWHMbQ5/qXgCuqyEIBFZou44n3x5XW/LQoA?= =?us-ascii?Q?16jL5q0El+jYpfTIjC0IB3/urI8E0LfETyimUE0YRYDWN04L+3BGP0vkPOOT?= =?us-ascii?Q?wZ5nDOZpIhbpA84+Kd4w9Xeh0lKCWAXGs1nDAQ9gMwXDvNhYnKRvUPbRVd7j?= =?us-ascii?Q?7po69wZ0y8i+qIBWirtLTe2JP0HxH+MvOFmcdj5EYndUIWnf+xbd1Xvk/6+3?= =?us-ascii?Q?WwNbw3b+NTS6aXE2NHQPeZ5ykgCzaOKsmAqKjhxQWblP4NEI7S0qx2yKiVEf?= =?us-ascii?Q?YQ82DodvBBD+cBNlMLdkOlkJT3ub5Dm8+bz0pubAgnnTggK6UN7dHgRp4KDJ?= =?us-ascii?Q?XbaEyLOng2JZIGHqBWUrwo/H+9OacDVmHy+GArdEu3chBr5M3cLjLzOxuFQq?= =?us-ascii?Q?jD6pMXilePNqGJPGdPV9tcGQyG4qlW2f9sKOT5riAfmGE0/OFajY1a2PGXQ5?= =?us-ascii?Q?e2+JP0FRf9FouaI+tMsp9/liMb+QzGgVlT4LrO7aOGe8fMwj3OhHRngIQMnG?= =?us-ascii?Q?UNElDtv2xZUayyBrXorluCMv+Zma4shu62Jowe83CO6fTHfUbo4b4cgjiW7G?= =?us-ascii?Q?a3ynGFCRCQSN8pF6ThfvN2wB4+APYnMfSSl9YkdiRoKsMros2KMwMbjngQpj?= =?us-ascii?Q?J44ljHm9KHoTRPuL9f66VoIb7YR/XxGfcdQlrtcKi+LL2NO0p1WHa4py/LYp?= =?us-ascii?Q?k5vfC/SedFiBoJvlyWjSiss5yvL7qCLi5DtoAdE3zNUeKVmMjQCfYdFrH7xc?= =?us-ascii?Q?9H0lLBSwdGScg0wpF2vHLnyj2AUzQm2hHTQMv6Aswp5yLvFy6WDIcZC3vYiB?= =?us-ascii?Q?I4WpzX18iLvPGA9gGdd3LBQg4U96kgef9i6YG557?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 60210087-e33e-4fd4-17c2-08ddfada05f5 X-MS-Exchange-CrossTenant-AuthSource: AS4PR04MB9621.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 19:47:26.8278 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6sk9ZAr3XUO5V+LouKxbqZs9fevWHl/5+bzDB0ju67Edq6Ujq0ItB3uGr2AP0KuD4joeBia8m9Xlz69R/eWoiA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR04MB7923 On Tue, Sep 23, 2025 at 08:12:27PM +0800, zhangsenchuan@eswincomputing.com wrote: > From: Senchuan Zhang > > Add driver for the Eswin EIC7700 PCIe host controller,the controller is > based on the DesignWare PCIe core, IP revision 6.00a The PCIe Gen.3 > controller supports a data rate of 8 GT/s and 4 channels, support INTX > and MSI interrupts. > > Signed-off-by: Yu Ning > Signed-off-by: Yanghui Ou > Signed-off-by: Senchuan Zhang > --- > drivers/pci/controller/dwc/Kconfig | 11 + > drivers/pci/controller/dwc/Makefile | 1 + > drivers/pci/controller/dwc/pcie-eic7700.c | 446 ++++++++++++++++++++++ > 3 files changed, 458 insertions(+) > create mode 100644 drivers/pci/controller/dwc/pcie-eic7700.c > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > index ff6b6d9e18ec..8474bc6356f7 100644 > --- a/drivers/pci/controller/dwc/Kconfig > +++ b/drivers/pci/controller/dwc/Kconfig > @@ -375,6 +375,17 @@ config PCI_EXYNOS > hardware and therefore the driver re-uses the DesignWare core > functions to implement the driver. > ... > + > +static void eswin_pcie_hide_broken_msix_cap(struct dw_pcie *pci) > +{ > + u16 offset, val; > + > + /* > + * Hardware doesn't support MSI-X but it advertises MSI-X capability, > + * to avoid this problem, the MSI-X capability in the PCIe capabilities > + * linked-list needs to be disabled. Since the PCI Express capability > + * structure's next pointer points to the MSI-X capability, and the > + * MSI-X capability's next pointer is null (00H), so only the PCI > + * Express capability structure's next pointer needs to be set 00H. > + */ > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + val = dw_pcie_readl_dbi(pci, offset); > + val &= ~PCIE_MSIX_DISABLE_MASK; supposed PCIE_MSIX_DISABLE_MASK is standard defination for PCI_CAP_ID_EXP register, it should be in pci.h > + dw_pcie_writel_dbi(pci, offset, val); > +} > + > +static int eswin_pcie_host_init(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct eswin_pcie *pcie = to_eswin_pcie(pci); > + struct eswin_pcie_port *port; > + u32 retries; > + u8 msi_cap; > + u32 val; > + int ret; > + > + pcie->num_clks = devm_clk_bulk_get_all_enabled(pci->dev, &pcie->clks); > + if (pcie->num_clks < 0) > + return dev_err_probe(pci->dev, pcie->num_clks, > + "Failed to get pcie clocks\n"); > + > + ret = eswin_pcie_deassert(pcie); > + if (ret) > + return ret; > + > + /* Configure root port type */ > + val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET); > + val &= ~PCIEMGMT_CTRL0_ROOT_PORT_MASK; > + writel_relaxed(val | PCI_EXP_TYPE_ROOT_PORT, > + pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET); > + > + list_for_each_entry(port, &pcie->ports, list) { > + ret = eswin_pcie_perst_deassert(port, pcie); > + if (ret) > + goto err_perst; > + } > + > + /* Configure app_hold_phy_rst */ > + val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET); > + val &= ~PCIEMGMT_APP_HOLD_PHY_RST; > + writel_relaxed(val, pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET); > + > + /* The maximum waiting time for the clock switch lock is 20ms */ > + retries = 20; > + do { > + val = readl_relaxed(pcie->mgmt_base + PCIEMGMT_STATUS0_OFFSET); > + if (!(val & PCIEMGMT_PM_SEL_AUX_CLK)) > + break; > + fsleep(1000); > + retries--; > + } while (retries); use readl_poll_timeout() > + > + if (!retries) { > + dev_err(pci->dev, "Timeout waiting for PM_SEL_AUX_CLK ready\n"); > + ret = -ETIMEDOUT; > + goto err_phy_init; > + } > + > + /* > + * Configure ESWIN VID:DID for Root Port as the default values are > + * invalid. > + */ > + dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, VENDOR_ID_VALUE); > + dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, DEVICE_ID_VALUE); > + > + /* Configure support 32 MSI vectors */ > + msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); > + val = dw_pcie_readw_dbi(pci, msi_cap + PCI_MSI_FLAGS); > + val &= ~PCI_MSI_FLAGS_QMASK; > + val |= FIELD_PREP(PCI_MSI_FLAGS_QMASK, 5); > + dw_pcie_writew_dbi(pci, msi_cap + PCI_MSI_FLAGS, val); > + > + /* Configure disable MSI-X cap */ > + if (!pcie->msix_cap) > + eswin_pcie_hide_broken_msix_cap(pci); > + > + return 0; > + > +err_phy_init: > + list_for_each_entry(port, &pcie->ports, list) > + reset_control_assert(port->perst); > +err_perst: > + eswin_pcie_assert(pcie); > + > + return ret; > +} > + ... > + > +static int eswin_pcie_suspend(struct device *dev) > +{ > + struct eswin_pcie *pcie = dev_get_drvdata(dev); > + struct eswin_pcie_port *port; > + > + /* > + * For controllers with active devices, resources are retained and > + * cannot be turned off. > + */ > + if (!dw_pcie_link_up(&pcie->pci)) { > + list_for_each_entry(port, &pcie->ports, list) > + reset_control_assert(port->perst); > + eswin_pcie_assert(pcie); > + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); > + pcie->suspended = true; > + } > + > + return 0; > +} does dw_pcie_resume_noirq() work for you? If not, please update common one. > + > +static int eswin_pcie_resume(struct device *dev) > +{ > + struct eswin_pcie *pcie = dev_get_drvdata(dev); > + int ret; > + > + if (!pcie->suspended) > + return 0; > + > + ret = eswin_pcie_host_init(&pcie->pci.pp); > + if (ret) { > + dev_err(dev, "Failed to init host: %d\n", ret); > + return ret; > + } > + > + dw_pcie_setup_rc(&pcie->pci.pp); > + eswin_pcie_start_link(&pcie->pci); > + dw_pcie_wait_for_link(&pcie->pci); > + > + pcie->suspended = false; > + > + return 0; > +} > + > +static const struct dev_pm_ops eswin_pcie_pm_ops = { > + NOIRQ_SYSTEM_SLEEP_PM_OPS(eswin_pcie_suspend, eswin_pcie_resume) > +}; > + > +static const struct eswin_pcie_data eswin_7700_data = { > + .msix_cap = false, > +}; > + > +static const struct of_device_id eswin_pcie_of_match[] = { > + { .compatible = "eswin,eic7700-pcie", .data = &eswin_7700_data }, > + {}, > +}; > + > +static struct platform_driver eswin_pcie_driver = { > + .probe = eswin_pcie_probe, > + .driver = { > + .name = "eic7700-pcie", > + .of_match_table = eswin_pcie_of_match, > + .suppress_bind_attrs = true, > + .pm = &eswin_pcie_pm_ops, > + }, > +}; > +builtin_platform_driver(eswin_pcie_driver); > + > +MODULE_DESCRIPTION("PCIe host controller driver for EIC7700 SoCs"); > +MODULE_AUTHOR("Yu Ning "); > +MODULE_AUTHOR("Senchuan Zhang "); > +MODULE_AUTHOR("Yanghui Ou "); > +MODULE_LICENSE("GPL"); > -- > 2.25.1 >