Re: [PATCH v2 4/9] drm/panthor: Implement optional reset

[Rain Yang <jiyu.yang@oss.nxp.com>]

On Thu, Sep 25, 2025 at 10:41:37PM +0200, Marek Vasut wrote:
>On 9/17/25 4:18 PM, Rain Yang wrote:
>
>Hello Jiyu,
>
>sorry for the late reply.
>
>> > > sorry for the inconvienence. this uboot version don't include SM-184's change.
>> > > I heard you're using i.MX95 A1 Chip, so you can extract the uboot in below link[1],
>> > > or build from source, or raise one ticket in this website[2].
>> > 
>> > I use mainline U-Boot 2025.07 with about 10 extra patches, but nothing
>> > significant. I don't think this is U-Boot issue, is it ?
>> > 
>> > I can rebuild SM, which commit in SM (from imx-sm repository) do I need to
>> > use ?
>> > 
>> > -- 
>> > Best regards,
>> > Marek Vasut
>> Hi Marek,
>> I think the problem may be about the multi power domain, the second power domain named perf
>> is for frequency change only, you can try to power on gpumix power domain only.
>
>I dropped that one.
>
>> as the 0x4d810008 is a write-once register and whose operation has been moved into the SM side,
>> so please drop the reset change.
>> can you also change the label of the gpu node from gpu to mali like "mali: gpu@4d900000",
>> as the internal driver use mali label to control the thermal up/low limitation.
>
>I updated all of the AHAB container, imx-oei and imx-sm components, and the
>reset controller is no longer needed indeed.

thanks, please update the gpu node label if possibly.

>
>> BTW, does the dynamic frequency work well on your side so far with perf domain?
>
>How do I test that ?

cat /sys/kernel/debug/clk/gpu/clk_rate, although its name in dts is core.
it is an read-only scmi-clk.
the clk rate should be fixed, as it can be changed only via scmi_perf in i.MX95.

>
>-- 
>Best regards,
>Marek Vasut