From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4912C19006B for ; Tue, 7 Oct 2025 12:33:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759840418; cv=none; b=q0sShjtp0tN0tCghZECFumzoxwNf1tdXaHz1ALnVX3uFiclmnnr0l7g2J3csBbKN1RR0LIYJw4Dg8eG3qLy9UnRz0C+S+Jy8/0i311sZYqB1L9oStBCddMjARGxgzDD28qZ8EStyLyOkBOIVsohniDl7k74HA1gyDLV6QyXQEB4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759840418; c=relaxed/simple; bh=DWZcXv4LGKuHQYrqbAmttjXhAkTF8/LAO+/rgtkGZWg=; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=rPqoxA2SrL1HlUxiBQtuWIlxL3krs0k3y0hvgjdthlsDcsq+Yf9xZ3ReMvXnJe1Ulk5KqSPxZgZhH7CJTt194Lc+1nK156eAWlPfQ96DihL1dhhQ/nQMWQwJd8K7rvImaQfgfYl/vJpAZGWN+auz0s6faJ2MypnKnKmt5oFT0dc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=unknown smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=tempfail smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 597CX1bh055627 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 7 Oct 2025 20:33:01 +0800 (+08) (envelope-from cl634@andestech.com) Received: from swlinux02 (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 7 Oct 2025 20:33:01 +0800 Date: Tue, 7 Oct 2025 20:33:01 +0800 From: CL Wang To: Conor Dooley CC: , , , , , , , , Subject: Re: [PATCH V1 1/2] dt-bindings: dmaengine: Add support for ATCDMAC300 DMA engine Message-ID: References: <20251002131659.973955-1-cl634@andestech.com> <20251002131659.973955-2-cl634@andestech.com> <20251002-absolute-spinning-f899e75b2c4a@spud> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20251002-absolute-spinning-f899e75b2c4a@spud> User-Agent: Mutt/2.2.12 (2023-09-09) X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 597CX1bh055627 Hi Conor, Thanks for your review. Yes, the DMA driver supports the Qilai platform. I have updated the DTS binding as shown below. Could you please take a look and let me know if anything still needs to be adjusted? properties: compatible: - const: andestech,atcdmac300 + oneOf: + - items: + - enum: + - andestech,qilai-dma + - const: andestech,atcdmac300 + - const: andestech,atcdmac300 ... dma-controller@f0c00000 { - compatible = "andestech,atcdmac300"; + compatible = "andestech,qilai-dma", "andestech,atcdmac300"; Thank you again for your feedback. Best regards, CL On Thu, Oct 02, 2025 at 07:40:35PM +0100, Conor Dooley wrote: > [EXTERNAL MAIL] > Date: Thu, 2 Oct 2025 19:40:35 +0100 > From: Conor Dooley > To: CL Wang > Cc: vkoul@kernel.org, dmaengine@vger.kernel.org, robh@kernel.org, > krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, > linux-kernel@vger.kernel.org, tim609@andestech.com > Subject: Re: [PATCH V1 1/2] dt-bindings: dmaengine: Add support for > ATCDMAC300 DMA engine > > On Thu, Oct 02, 2025 at 09:16:58PM +0800, CL Wang wrote: > > Document devicetree bindings for Andes ATCDMAC300 DMA engine > > > > Signed-off-by: CL Wang > > --- > > .../bindings/dma/andestech,atcdmac300.yaml | 51 +++++++++++++++++++ > > MAINTAINERS | 6 +++ > > 2 files changed, 57 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/dma/andestech,atcdmac300.yaml > > > > diff --git a/Documentation/devicetree/bindings/dma/andestech,atcdmac300.yaml b/Documentation/devicetree/bindings/dma/andestech,atcdmac300.yaml > > new file mode 100644 > > index 000000000000..769694616517 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/dma/andestech,atcdmac300.yaml > > @@ -0,0 +1,51 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/dma/andestech,atcdmac300.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Andes ATCDMAC300 DMA Controller > > + > > +maintainers: > > + - CL Wang > > + > > +allOf: > > + - $ref: dma-controller.yaml# > > + > > +properties: > > + compatible: > > + const: andestech,atcdmac300 > > "atcdmac300" sounds like the name of an IP block. What platforms are > actually using this? They should have platform-specific compatibles, for > example, "andestech,qilai-dma" if that's the platform where this is > supported. > > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + "#dma-cells": > > + const: 1 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - "#dma-cells" > > + > > +unevaluatedProperties: false > > + > > +examples: > > + - | > > + #include > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + dma-controller@f0c00000 { > > + compatible = "andestech,atcdmac300"; > > + reg = <0x0 0xf0c00000 0x0 0x1000>; > > + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; > > + #dma-cells = <1>; > > + }; > > + }; > > +... > > diff --git a/MAINTAINERS b/MAINTAINERS > > index fe168477caa4..dd3272cdadd6 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -1778,6 +1778,12 @@ S: Supported > > F: drivers/clk/analogbits/* > > F: include/linux/clk/analogbits* > > > > +ANDES DMA DRIVER > > +M: CL Wang > > +S: Supported > > +F: Documentation/devicetree/bindings/dma/andestech,atcdmac300.yaml > > +F: drivers/dma/atcdmac300* > > + > > ANDROID DRIVERS > > M: Greg Kroah-Hartman > > M: Arve Hjønnevåg > > -- > > 2.34.1 > >