[PATCH v4 0/3] RISC-V: Detect Ssqosid extension and handle srmcfg CSR

[PATCH v4 0/3] RISC-V: Detect Ssqosid extension and handle srmcfg CSR

[Drew Fustini]

This series adds support for the RISC-V Quality-of-Service Identifiers
(Ssqosid) extension [1] which adds the srmcfg register. This CSR
configures a hart with two identifiers: a Resource Control ID (RCID)
and a Monitoring Counter ID (MCID). These identifiers accompany each
request issued by the hart to shared resource controllers.

Background on RISC-V QoS:

The Ssqosid extension is used by the RISC-V Capacity and Bandwidth
Controller QoS Register Interface (CBQRI) specification [2]. QoS in
this context is concerned with shared resources on an SoC such as cache
capacity and memory bandwidth. Intel and AMD already have QoS features
on x86 and ARM has MPAM. There is an existing user interface in Linux:
the resctrl virtual filesystem [3].

The srmcfg CSR provides a mechanism by which a software workload (e.g.
a process or a set of processes) can be associated with an RCID and an
MCID. CBQRI defines operations to configure resource usage limits, in
the form of capacity or bandwidth. CBQRI also defines operations to
configure counters to track the resource utilization.

Goal for this series:

These patches are taken from the implementation of resctrl support for
RISC-V CBQRI. Please refer to the proof-of-concept RFC [4] for details
on the resctrl implementation. More recently, I have rebased the CBQRI
support on mainline [5]. Big thanks to James Morse for the tireless
work to extract resctrl from arch/x86 and make it available to all
architectures.

I think it makes sense to first focus on the detection of Ssqosid and
handling of srmcfg when switching tasks. It has been tested against a
QEMU branch that implements Ssqosid and CBQRI [6]. A test driver [7]
was used to set srmcfg for the current process. This allows switch_to
to be tested without resctrl.

[1] https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
[2] https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0
[3] https://docs.kernel.org/filesystems/resctrl.html
[4] https://lore.kernel.org/linux-riscv/20230419111111.477118-1-dfustini@baylibre.com/
[5] https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git/log/?h=b4/cbqri
[6] https://github.com/tt-fustini/qemu/tree/riscv-cbqri-rqsc-pptt
[7] https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git/log/?h=b4/ssqosid-debug

Changes in v4:
 - Rebase on riscv/for-next as of riscv-for-linus-6.18-mw2
 - Add Conor's Acked-by to the yaml patch
 - Link to v3: https://lore.kernel.org/all/20250920-ssqosid-v6-17-rc5-v3-0-5093162922d8@kernel.org/

Changes in v3:
 - Fix parameter in __switch_to_srmcfg() when CONFIG_RISCV_ISA_SSQOSID
   is not set to avoid error in clang. This does trigger checkpatch
   warning about "Argument '__next' is not used in function-like macro"
   but it seems that '__switch_to_srmcfg(__next)' is needed to avoid
   the error that LKP reported. '__switch_to_srmcfg()' will trigger a
   build error in clang.
   https://lore.kernel.org/oe-kbuild-all/202509162355.wByessnb-lkp@intel.com/
 - Improve description of ssqosid in extensions.xml
 - Link to v2: https://lore.kernel.org/linux-riscv/20250915-ssqosid-v6-17-rc5-v2-0-2d4b0254dfd6@kernel.org/

Changes in v2:
 - Restore the per-cpu fix from RFC v2 that was missed in v1:
   change DEFINE_PER_CPU to DECLARE_PER_CPU in qos.h and move
   DEFINE_PER_CPU to qos.c
 - Introduce a patch that adds Ssqosid to riscv/extensions.yaml
 - Link to v1: https://lore.kernel.org/r/20250910-ssqosid-v6-17-rc5-v1-0-72cb8f144615@kernel.org

Changes in v1:
 - Rename all instances of the sqoscfg CSR to srmcfg to match the
   ratified Ssqosid spec
 - Link RFC v2: https://lore.kernel.org/linux-riscv/20230430-riscv-cbqri-rfc-v2-v2-0-8e3725c4a473@baylibre.com/

Changes in RFC v2:
 - change DEFINE_PER_CPU to DECLARE_PER_CPU for cpu_sqoscfg in qos.h to
   prevent linking error about multiple definition. Move DEFINE_PER_CPU
   for cpu_sqoscfg into qos.c
 - renamed qos prefix in function names to sqoscfg to be less generic
 - handle sqoscfg the same way has_vector and has_fpu are handled in the
   vector patch series
 - Link to RFC v1: https://lore.kernel.org/linux-riscv/20230410043646.3138446-1-dfustini@baylibre.com/

Signed-off-by: Drew Fustini <fustini@kernel.org>
---
Drew Fustini (3):
      dt-bindings: riscv: Add Ssqosid extension description
      RISC-V: Detect the Ssqosid extension
      RISC-V: Add support for srmcfg CSR from Ssqosid ext

 .../devicetree/bindings/riscv/extensions.yaml      |  6 ++++
 MAINTAINERS                                        |  7 ++++
 arch/riscv/Kconfig                                 | 17 +++++++++
 arch/riscv/include/asm/csr.h                       |  8 +++++
 arch/riscv/include/asm/hwcap.h                     |  1 +
 arch/riscv/include/asm/processor.h                 |  3 ++
 arch/riscv/include/asm/qos.h                       | 41 ++++++++++++++++++++++
 arch/riscv/include/asm/switch_to.h                 |  3 ++
 arch/riscv/kernel/Makefile                         |  2 ++
 arch/riscv/kernel/cpufeature.c                     |  1 +
 arch/riscv/kernel/qos/Makefile                     |  2 ++
 arch/riscv/kernel/qos/qos.c                        |  5 +++
 12 files changed, 96 insertions(+)
---
base-commit: 68247d45c045bb7dda923cf2c8d0937ce0e16394
change-id: 20251007-ssqosid-ddc87968b2d9

Best regards,
-- 
Drew Fustini <fustini@kernel.org>

[PATCH v4 1/3] dt-bindings: riscv: Add Ssqosid extension description

[Drew Fustini]

Document the ratified Supervisor-mode Quality of Service ID (Ssqosid)
extension v1.0.

Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Drew Fustini <fustini@kernel.org>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index de41a6f074d3af2ceaf5293dfe75d16f43d416d6..27d0efe72e0fa436c0796550ef126f1f17c36541 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -165,6 +165,12 @@ properties:
             ratified at commit d70011dde6c2 ("Update to ratified state")
             of riscv-j-extension.
 
+        - const: ssqosid
+          description: |
+            The Ssqosid extension for Quality of Service ID is ratified
+            as v1.0 in commit 5059e0ca641c  ("Merge pull request #7 from
+            ved-rivos/Ratified") of riscv-ssqosid.
+
         - const: sstc
           description: |
             The standard Sstc supervisor-level extension for time compare as

-- 
2.34.1

[PATCH v4 2/3] RISC-V: Detect the Ssqosid extension

[Drew Fustini]

Ssqosid is the RISC-V Quality-of-Service (QoS) Identifiers specification
which defines the Supervisor Resource Management Configuration (srmcfg)
register.

Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
Signed-off-by: Kornel Dulęba <mindal@semihalf.com>
[fustini: rebase on riscv/for-next]
Signed-off-by: Drew Fustini <fustini@kernel.org>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index affd63e11b0a344c33a73647351ac02a94e42981..b4239f4f092d036ee3d037177b990e317d34a77f 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -106,6 +106,7 @@
 #define RISCV_ISA_EXT_ZAAMO		97
 #define RISCV_ISA_EXT_ZALRSC		98
 #define RISCV_ISA_EXT_ZICBOP		99
+#define RISCV_ISA_EXT_SSQOSID		100
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 67b59699357da8010db919b4ea2c24cd0d51182a..aeb14028bd91aa62bab854c87a11e20bdb848364 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -533,6 +533,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
 	__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
+	__RISCV_ISA_EXT_DATA(ssqosid, RISCV_ISA_EXT_SSQOSID),
 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
 	__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
 	__RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),

-- 
2.34.1

[PATCH v4 3/3] RISC-V: Add support for srmcfg CSR from Ssqosid ext

[Drew Fustini]

Add support for the srmcfg CSR defined in the Ssqosid ISA extension
(Supervisor-mode Quality of Service ID). The CSR contains two fields:

  - Resource Control ID (RCID) used determine resource allocation
  - Monitoring Counter ID (MCID) used to track resource usage

Requests from a hart to shared resources like cache will be tagged with
these IDs. This allows the usage of shared resources to be associated
with the task currently running on the hart.

A srmcfg field is added to thread_struct and has the same format as the
srmcfg CSR. This allows the scheduler to set the hart's srmcfg CSR to
contain the RCID and MCID for the task that is being scheduled in. The
srmcfg CSR is only written to if the thread_struct.srmcfg is different
than the current value of the CSR.

A per-cpu variable cpu_srmcfg is used to mirror that state of the CSR.
This is because access to L1D hot memory should be several times faster
than a CSR read. Also, in the case of virtualization, accesses to this
CSR are trapped in the hypervisor.

Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
Co-developed-by: Kornel Dulęba <mindal@semihalf.com>
Signed-off-by: Kornel Dulęba <mindal@semihalf.com>
[fustini: rename csr, refactor switch_to, rebase on riscv/for-next]
Signed-off-by: Drew Fustini <fustini@kernel.org>
---
 MAINTAINERS                        |  7 +++++++
 arch/riscv/Kconfig                 | 17 ++++++++++++++++
 arch/riscv/include/asm/csr.h       |  8 ++++++++
 arch/riscv/include/asm/processor.h |  3 +++
 arch/riscv/include/asm/qos.h       | 41 ++++++++++++++++++++++++++++++++++++++
 arch/riscv/include/asm/switch_to.h |  3 +++
 arch/riscv/kernel/Makefile         |  2 ++
 arch/riscv/kernel/qos/Makefile     |  2 ++
 arch/riscv/kernel/qos/qos.c        |  5 +++++
 9 files changed, 88 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 858de646632acf2ba900b799882f6aa79a1df6fa..315feed291e5b7417633f0ffdf8b5abb50b6c831 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21700,6 +21700,13 @@ F:	drivers/perf/riscv_pmu.c
 F:	drivers/perf/riscv_pmu_legacy.c
 F:	drivers/perf/riscv_pmu_sbi.c
 
+RISC-V QOS RESCTRL SUPPORT
+M:	Drew Fustini <fustini@kernel.org>
+L:	linux-riscv@lists.infradead.org
+S:	Supported
+F:	arch/riscv/include/asm/qos.h
+F:	arch/riscv/kernel/qos/
+
 RISC-V RPMI AND MPXY DRIVERS
 M:	Rahul Pathak <rahul@summations.net>
 M:	Anup Patel <anup@brainfault.org>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 715e59f1e287dcdbbf3ae0dd8dac2a80e3fe9143..e41abf303794cf5d236337304148c80ee98a359c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -606,6 +606,23 @@ config RISCV_ISA_SVNAPOT
 
 	  If you don't know what to do here, say Y.
 
+config RISCV_ISA_SSQOSID
+	bool "Ssqosid extension support for supervisor mode Quality of Service ID"
+	default y
+	help
+	  Adds support for the Ssqosid ISA extension (Supervisor-mode
+	  Quality of Service ID).
+
+	  Ssqosid defines the srmcfg CSR which allows the system to tag the
+	  running process with an RCID (Resource Control ID) and MCID
+	  (Monitoring Counter ID). The RCID is used to determine resource
+	  allocation. The MCID is used to track resource usage in event
+	  counters.
+
+	  For example, a cache controller may use the RCID to apply a
+	  cache partitioning scheme and use the MCID to track how much
+	  cache a process, or a group of processes, is using.
+
 config RISCV_ISA_SVPBMT
 	bool "Svpbmt extension support for supervisor mode page-based memory types"
 	depends on 64BIT && MMU
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 4a37a98398ad3b527c280c1e1260d0b53a4ac8d9..2590b89b8f721a4f98a850d4640aa571a7ec80d1 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -75,6 +75,13 @@
 #define SATP_ASID_MASK	_AC(0xFFFF, UL)
 #endif
 
+/* SRMCFG fields */
+#define SRMCFG_RCID_MASK	_AC(0x00000FFF, UL)
+#define SRMCFG_MCID_MASK	SRMCFG_RCID_MASK
+#define SRMCFG_MCID_SHIFT	16
+#define SRMCFG_MASK		((SRMCFG_MCID_MASK << SRMCFG_MCID_SHIFT) | \
+				  SRMCFG_RCID_MASK)
+
 /* Exception cause high bit - is an interrupt if set */
 #define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
 
@@ -317,6 +324,7 @@
 #define CSR_STVAL		0x143
 #define CSR_SIP			0x144
 #define CSR_SATP		0x180
+#define CSR_SRMCFG		0x181
 
 #define CSR_STIMECMP		0x14D
 #define CSR_STIMECMPH		0x15D
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index da5426122d280b53b8ba8f764ea6f1b9f93ca994..183c55e32b9656d34fb60cdf9bc61162fa25d165 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -122,6 +122,9 @@ struct thread_struct {
 	/* A forced icache flush is not needed if migrating to the previous cpu. */
 	unsigned int prev_cpu;
 #endif
+#ifdef CONFIG_RISCV_ISA_SSQOSID
+	u32 srmcfg;
+#endif
 };
 
 /* Whitelist the fstate from the task_struct for hardened usercopy */
diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h
new file mode 100644
index 0000000000000000000000000000000000000000..84830d7c6dc4a1fce86d514ed5af97be32a26630
--- /dev/null
+++ b/arch/riscv/include/asm/qos.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_RISCV_QOS_H
+#define _ASM_RISCV_QOS_H
+
+#ifdef CONFIG_RISCV_ISA_SSQOSID
+
+#include <linux/sched.h>
+#include <linux/jump_label.h>
+
+#include <asm/barrier.h>
+#include <asm/csr.h>
+#include <asm/hwcap.h>
+
+/* cached value of srmcfg csr for each cpu */
+DECLARE_PER_CPU(u32, cpu_srmcfg);
+
+static inline void __switch_to_srmcfg(struct task_struct *next)
+{
+	u32 *cpu_srmcfg_ptr = this_cpu_ptr(&cpu_srmcfg);
+	u32 thread_srmcfg;
+
+	thread_srmcfg = READ_ONCE(next->thread.srmcfg);
+
+	if (thread_srmcfg != *cpu_srmcfg_ptr) {
+		*cpu_srmcfg_ptr = thread_srmcfg;
+		csr_write(CSR_SRMCFG, thread_srmcfg);
+	}
+}
+
+static __always_inline bool has_srmcfg(void)
+{
+	return riscv_has_extension_unlikely(RISCV_ISA_EXT_SSQOSID);
+}
+
+#else /* ! CONFIG_RISCV_ISA_SSQOSID  */
+
+static __always_inline bool has_srmcfg(void) { return false; }
+#define __switch_to_srmcfg(__next) do { } while (0)
+
+#endif /* CONFIG_RISCV_ISA_SSQOSID */
+#endif /* _ASM_RISCV_QOS_H */
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 0e71eb82f920cac2f14bb626879bb219a2f247cc..a684a3795d3d7f5e027ec0a83c30afd1a18d7228 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -14,6 +14,7 @@
 #include <asm/processor.h>
 #include <asm/ptrace.h>
 #include <asm/csr.h>
+#include <asm/qos.h>
 
 #ifdef CONFIG_FPU
 extern void __fstate_save(struct task_struct *save_to);
@@ -119,6 +120,8 @@ do {							\
 		__switch_to_fpu(__prev, __next);	\
 	if (has_vector() || has_xtheadvector())		\
 		__switch_to_vector(__prev, __next);	\
+	if (has_srmcfg())				\
+		__switch_to_srmcfg(__next);	\
 	if (switch_to_should_flush_icache(__next))	\
 		local_flush_icache_all();		\
 	__switch_to_envcfg(__next);			\
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index c7b542573407c813a4a45fe9bf78a676599c0503..0108a4e6338a7972b6805ef14048d4e5e8833d82 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -125,3 +125,5 @@ obj-$(CONFIG_ACPI)		+= acpi.o
 obj-$(CONFIG_ACPI_NUMA)	+= acpi_numa.o
 
 obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) += bugs.o
+
+obj-$(CONFIG_RISCV_ISA_SSQOSID) += qos/
diff --git a/arch/riscv/kernel/qos/Makefile b/arch/riscv/kernel/qos/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..9f996263a86d7e2e410890d2425e74b2277a57ad
--- /dev/null
+++ b/arch/riscv/kernel/qos/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_RISCV_ISA_SSQOSID) += qos.o
diff --git a/arch/riscv/kernel/qos/qos.c b/arch/riscv/kernel/qos/qos.c
new file mode 100644
index 0000000000000000000000000000000000000000..7b06f7ae9056b8f2eb53a0eecf5a6512edc29fbe
--- /dev/null
+++ b/arch/riscv/kernel/qos/qos.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <asm/qos.h>
+
+/* cached value of sqoscfg csr for each cpu */
+DEFINE_PER_CPU(u32, cpu_srmcfg);

-- 
2.34.1

Re: [PATCH v4 3/3] RISC-V: Add support for srmcfg CSR from Ssqosid ext

[Radim Krčmář]

2025-10-07T23:21:12-07:00, Drew Fustini <fustini@kernel.org>:
> diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h
> +static inline void __switch_to_srmcfg(struct task_struct *next)
> +{
> +	u32 *cpu_srmcfg_ptr = this_cpu_ptr(&cpu_srmcfg);
> +	u32 thread_srmcfg;
> +
> +	thread_srmcfg = READ_ONCE(next->thread.srmcfg);
> +
> +	if (thread_srmcfg != *cpu_srmcfg_ptr) {

Wouldn't prev->thread.srmcfg have the value of CSR_SRMCFG when executing
switch_to?

Thanks.

> +		*cpu_srmcfg_ptr = thread_srmcfg;
> +		csr_write(CSR_SRMCFG, thread_srmcfg);
> +	}
> +}

Re: [External] [PATCH v4 0/3] RISC-V: Detect Ssqosid extension and handle srmcfg CSR

[yunhui cui]

Hi Drew,

On Wed, Oct 8, 2025 at 2:22 PM Drew Fustini <fustini@kernel.org> wrote:
>
> This series adds support for the RISC-V Quality-of-Service Identifiers
> (Ssqosid) extension [1] which adds the srmcfg register. This CSR
> configures a hart with two identifiers: a Resource Control ID (RCID)
> and a Monitoring Counter ID (MCID). These identifiers accompany each
> request issued by the hart to shared resource controllers.
>
> Background on RISC-V QoS:
>
> The Ssqosid extension is used by the RISC-V Capacity and Bandwidth
> Controller QoS Register Interface (CBQRI) specification [2]. QoS in
> this context is concerned with shared resources on an SoC such as cache
> capacity and memory bandwidth. Intel and AMD already have QoS features
> on x86 and ARM has MPAM. There is an existing user interface in Linux:
> the resctrl virtual filesystem [3].
>
> The srmcfg CSR provides a mechanism by which a software workload (e.g.
> a process or a set of processes) can be associated with an RCID and an
> MCID. CBQRI defines operations to configure resource usage limits, in
> the form of capacity or bandwidth. CBQRI also defines operations to
> configure counters to track the resource utilization.
>
> Goal for this series:
>
> These patches are taken from the implementation of resctrl support for
> RISC-V CBQRI. Please refer to the proof-of-concept RFC [4] for details
> on the resctrl implementation. More recently, I have rebased the CBQRI
> support on mainline [5]. Big thanks to James Morse for the tireless
> work to extract resctrl from arch/x86 and make it available to all
> architectures.
>
> I think it makes sense to first focus on the detection of Ssqosid and
> handling of srmcfg when switching tasks. It has been tested against a
> QEMU branch that implements Ssqosid and CBQRI [6]. A test driver [7]
> was used to set srmcfg for the current process. This allows switch_to
> to be tested without resctrl.

Could we consider submitting the entire QoS functionality as a single
integrated patchset (indicating the upstream branch that the patchset
is based on)? This should include the content from
https://lore.kernel.org/linux-riscv/20230419111111.477118-1-dfustini@baylibre.com/


>
> [1] https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
> [2] https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0
> [3] https://docs.kernel.org/filesystems/resctrl.html
> [4] https://lore.kernel.org/linux-riscv/20230419111111.477118-1-dfustini@baylibre.com/
> [5] https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git/log/?h=b4/cbqri
> [6] https://github.com/tt-fustini/qemu/tree/riscv-cbqri-rqsc-pptt
> [7] https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git/log/?h=b4/ssqosid-debug
>
> Changes in v4:
>  - Rebase on riscv/for-next as of riscv-for-linus-6.18-mw2
>  - Add Conor's Acked-by to the yaml patch
>  - Link to v3: https://lore.kernel.org/all/20250920-ssqosid-v6-17-rc5-v3-0-5093162922d8@kernel.org/
>
> Changes in v3:
>  - Fix parameter in __switch_to_srmcfg() when CONFIG_RISCV_ISA_SSQOSID
>    is not set to avoid error in clang. This does trigger checkpatch
>    warning about "Argument '__next' is not used in function-like macro"
>    but it seems that '__switch_to_srmcfg(__next)' is needed to avoid
>    the error that LKP reported. '__switch_to_srmcfg()' will trigger a
>    build error in clang.
>    https://lore.kernel.org/oe-kbuild-all/202509162355.wByessnb-lkp@intel.com/
>  - Improve description of ssqosid in extensions.xml
>  - Link to v2: https://lore.kernel.org/linux-riscv/20250915-ssqosid-v6-17-rc5-v2-0-2d4b0254dfd6@kernel.org/
>
> Changes in v2:
>  - Restore the per-cpu fix from RFC v2 that was missed in v1:
>    change DEFINE_PER_CPU to DECLARE_PER_CPU in qos.h and move
>    DEFINE_PER_CPU to qos.c
>  - Introduce a patch that adds Ssqosid to riscv/extensions.yaml
>  - Link to v1: https://lore.kernel.org/r/20250910-ssqosid-v6-17-rc5-v1-0-72cb8f144615@kernel.org
>
> Changes in v1:
>  - Rename all instances of the sqoscfg CSR to srmcfg to match the
>    ratified Ssqosid spec
>  - Link RFC v2: https://lore.kernel.org/linux-riscv/20230430-riscv-cbqri-rfc-v2-v2-0-8e3725c4a473@baylibre.com/
>
> Changes in RFC v2:
>  - change DEFINE_PER_CPU to DECLARE_PER_CPU for cpu_sqoscfg in qos.h to
>    prevent linking error about multiple definition. Move DEFINE_PER_CPU
>    for cpu_sqoscfg into qos.c
>  - renamed qos prefix in function names to sqoscfg to be less generic
>  - handle sqoscfg the same way has_vector and has_fpu are handled in the
>    vector patch series
>  - Link to RFC v1: https://lore.kernel.org/linux-riscv/20230410043646.3138446-1-dfustini@baylibre.com/
>
> Signed-off-by: Drew Fustini <fustini@kernel.org>
> ---
> Drew Fustini (3):
>       dt-bindings: riscv: Add Ssqosid extension description
>       RISC-V: Detect the Ssqosid extension
>       RISC-V: Add support for srmcfg CSR from Ssqosid ext
>
>  .../devicetree/bindings/riscv/extensions.yaml      |  6 ++++
>  MAINTAINERS                                        |  7 ++++
>  arch/riscv/Kconfig                                 | 17 +++++++++
>  arch/riscv/include/asm/csr.h                       |  8 +++++
>  arch/riscv/include/asm/hwcap.h                     |  1 +
>  arch/riscv/include/asm/processor.h                 |  3 ++
>  arch/riscv/include/asm/qos.h                       | 41 ++++++++++++++++++++++
>  arch/riscv/include/asm/switch_to.h                 |  3 ++
>  arch/riscv/kernel/Makefile                         |  2 ++
>  arch/riscv/kernel/cpufeature.c                     |  1 +
>  arch/riscv/kernel/qos/Makefile                     |  2 ++
>  arch/riscv/kernel/qos/qos.c                        |  5 +++
>  12 files changed, 96 insertions(+)
> ---
> base-commit: 68247d45c045bb7dda923cf2c8d0937ce0e16394
> change-id: 20251007-ssqosid-ddc87968b2d9
>
> Best regards,
> --
> Drew Fustini <fustini@kernel.org>
>
>

Thanks,
Yunhui

Re: [External] [PATCH v4 0/3] RISC-V: Detect Ssqosid extension and handle srmcfg CSR

[Drew Fustini]

On Fri, Oct 10, 2025 at 08:23:50PM +0800, yunhui cui wrote:
> Hi Drew,
[snip]
> > I think it makes sense to first focus on the detection of Ssqosid and
> > handling of srmcfg when switching tasks. It has been tested against a
> > QEMU branch that implements Ssqosid and CBQRI [6]. A test driver [7]
> > was used to set srmcfg for the current process. This allows switch_to
> > to be tested without resctrl.
> 
> Could we consider submitting the entire QoS functionality as a single
> integrated patchset (indicating the upstream branch that the patchset
> is based on)? This should include the content from
> https://lore.kernel.org/linux-riscv/20230419111111.477118-1-dfustini@baylibre.com/

Thanks for the feedback. I had thought that submitting Ssqosid
separately would streamline the review of the parts that most affects
existing arch/riscv code (like switch_to.h) before adding code for CBQRI
and resctrl integration.

But I have gotten similar feedback from another person too. I can post a
complete series that adds Ssqosid and CBQRI support including the
resctrl interface. I have a cbqri branch [1] on top of riscv/for-next.
I need to clean up some of the code, and then I can send a series with
ssqosid+cbqri.

That cbqri branch just has device tree support in order to demonstrate
the resctrl functionality. However, I did also work on support for the
ACPI RQSC table earlier this year for a proof of concept [2]. I have
been thinking that I will hold back the ACPI support until after Ssqosid
and CBQRI support is reviewed. It also depends on some improvements
regarding the ACPI PPTT table that James Morse is currently working on for
ARM MPAM support [3].

Thanks,
Drew

[1] https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git/log/?h=b4/cbqri
[2] https://lf-rise.atlassian.net/wiki/spaces/HOME/pages/433291272/ACPI+RQSC+Proof+of+Concept
[3] https://lore.kernel.org/all/20250910204309.20751-1-james.morse@arm.com/

Re: [PATCH v4 3/3] RISC-V: Add support for srmcfg CSR from Ssqosid ext

[Drew Fustini]

On Thu, Oct 09, 2025 at 08:47:27AM +0200, Radim Krčmář wrote:
> 2025-10-07T23:21:12-07:00, Drew Fustini <fustini@kernel.org>:
> > diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h
> > +static inline void __switch_to_srmcfg(struct task_struct *next)
> > +{
> > +	u32 *cpu_srmcfg_ptr = this_cpu_ptr(&cpu_srmcfg);
> > +	u32 thread_srmcfg;
> > +
> > +	thread_srmcfg = READ_ONCE(next->thread.srmcfg);
> > +
> > +	if (thread_srmcfg != *cpu_srmcfg_ptr) {
> 
> Wouldn't prev->thread.srmcfg have the value of CSR_SRMCFG when executing
> switch_to?

Thanks for reviewing. Yes, you are right that prev->thread.srmcfg should
have same value as CSR_SRMCFG. Are you suggesting that the cpu_srmcfg is
not necessary as prev->thread.srmcfg should have same value?

Drew

Re: [PATCH v4 3/3] RISC-V: Add support for srmcfg CSR from Ssqosid ext

[Radim Krčmář]

2025-10-11T11:35:46-07:00, Drew Fustini <fustini@kernel.org>:
> On Thu, Oct 09, 2025 at 08:47:27AM +0200, Radim Krčmář wrote:
>> 2025-10-07T23:21:12-07:00, Drew Fustini <fustini@kernel.org>:
>> > diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h
>> > +static inline void __switch_to_srmcfg(struct task_struct *next)
>> > +{
>> > +	u32 *cpu_srmcfg_ptr = this_cpu_ptr(&cpu_srmcfg);
>> > +	u32 thread_srmcfg;
>> > +
>> > +	thread_srmcfg = READ_ONCE(next->thread.srmcfg);
>> > +
>> > +	if (thread_srmcfg != *cpu_srmcfg_ptr) {
>> 
>> Wouldn't prev->thread.srmcfg have the value of CSR_SRMCFG when executing
>> switch_to?
>
> Thanks for reviewing. Yes, you are right that prev->thread.srmcfg should
> have same value as CSR_SRMCFG. Are you suggesting that the cpu_srmcfg is
> not necessary as prev->thread.srmcfg should have same value?

Yes, it would be more consistent with other context switched state.
I just wasn't sure if srmcfg doesn't have special race conditions.

Thanks.

Re: [PATCH v4 3/3] RISC-V: Add support for srmcfg CSR from Ssqosid ext

[Drew Fustini]

On Mon, Oct 13, 2025 at 11:06:50AM +0200, Radim Krčmář wrote:
> 2025-10-11T11:35:46-07:00, Drew Fustini <fustini@kernel.org>:
> > On Thu, Oct 09, 2025 at 08:47:27AM +0200, Radim Krčmář wrote:
> >> 2025-10-07T23:21:12-07:00, Drew Fustini <fustini@kernel.org>:
> >> > diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h
> >> > +static inline void __switch_to_srmcfg(struct task_struct *next)
> >> > +{
> >> > +	u32 *cpu_srmcfg_ptr = this_cpu_ptr(&cpu_srmcfg);
> >> > +	u32 thread_srmcfg;
> >> > +
> >> > +	thread_srmcfg = READ_ONCE(next->thread.srmcfg);
> >> > +
> >> > +	if (thread_srmcfg != *cpu_srmcfg_ptr) {
> >> 
> >> Wouldn't prev->thread.srmcfg have the value of CSR_SRMCFG when executing
> >> switch_to?
> >
> > Thanks for reviewing. Yes, you are right that prev->thread.srmcfg should
> > have same value as CSR_SRMCFG. Are you suggesting that the cpu_srmcfg is
> > not necessary as prev->thread.srmcfg should have same value?
> 
> Yes, it would be more consistent with other context switched state.
> I just wasn't sure if srmcfg doesn't have special race conditions.

I did some testing and the per-cpu cache of CSR_SRMCFG is needed. This
is because thread.srmcfg is changed asynchronously from when CSR_SRMCFG
is updated in __switch_to_srmcfg.

The srmcfg value for a thread is updated when a user writes the pid to a
control group's tasks file in the resctrl virtual filesystem:

void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32 rmid)
{
       u32 srmcfg;

       WARN_ON_ONCE((closid & SRMCFG_RCID_MASK) != closid);
       WARN_ON_ONCE((rmid & SRMCFG_MCID_MASK) != rmid);

       srmcfg = rmid << SRMCFG_MCID_SHIFT;
       srmcfg |= closid;
       WRITE_ONCE(tsk->thread.srmcfg, srmcfg);
}

I'm getting a full patch series ready that has both the Ssqosid and the
CBQRI resctrl patches, and I will post that soon. I'm also preparing
a freshly rebased Qemu series that adds the CBQRI controllers.

Thanks,
Drew