From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Andrew Lunn <andrew@lunn.ch>,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
Daniel Scally <dan.scally@ideasonboard.com>,
Kieran Bingham <kieran.bingham@ideasonboard.com>,
Stefan Klug <stefan.klug@ideasonboard.com>,
Conor Dooley <conor+dt@kernel.org>,
Fabio Estevam <festevam@gmail.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Rob Herring <robh@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>
Subject: Re: [PATCH] arm64: dts: imx8mp-debix-model-a: Disable EEE for 1000T
Date: Mon, 27 Oct 2025 11:22:35 +0000 [thread overview]
Message-ID: <aP9V-zosjg7rY5vZ@shell.armlinux.org.uk> (raw)
In-Reply-To: <20251027072749.GA7811@pendragon.ideasonboard.com>
On Mon, Oct 27, 2025 at 09:27:49AM +0200, Laurent Pinchart wrote:
> I've tried to diagnose the issue by adding interrupt counters to
> dwmac4_irq_status(), counting interrupts for each bit of GMAC_INT_STATUS
> (0x00b0). Bit RGSMIIIS (0) is the only one that seems linked to the
> interrupts storm, increasing at around 10k per second. However, the
> corresponding bit in GMAC_INT_EN (0x00b4) is *not* set.
I'll add to my comments earlier, because it may help you work out
what's going on.
RGSMIIS will be set when the LNKSTS bit (bit 19) of 0xf8 changes
state. RGSMIIS is only cleared by reading this register. So, something
else to test would be to do a dummy read of this register and see
whether the interrupt storm still has the RGSMIIS bit set.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
next prev parent reply other threads:[~2025-10-27 11:22 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-26 12:29 [PATCH] arm64: dts: imx8mp-debix-model-a: Disable EEE for 1000T Laurent Pinchart
2025-10-27 1:31 ` Fabio Estevam
2025-10-27 3:08 ` Andrew Lunn
2025-10-27 7:27 ` Laurent Pinchart
2025-10-27 8:47 ` Emanuele Ghidoli
2025-10-27 9:00 ` Russell King (Oracle)
2025-10-27 9:18 ` Emanuele Ghidoli
2025-10-27 9:32 ` Russell King (Oracle)
2025-10-27 23:08 ` Laurent Pinchart
2025-10-27 11:22 ` Russell King (Oracle) [this message]
2025-10-27 23:15 ` Laurent Pinchart
2025-10-27 9:12 ` Oleksij Rempel
2025-10-27 10:02 ` Laurent Pinchart
2025-10-27 10:23 ` Oleksij Rempel
2025-10-27 10:31 ` Laurent Pinchart
2025-10-27 10:34 ` Russell King (Oracle)
2025-10-27 10:44 ` Oleksij Rempel
2025-10-27 10:48 ` Russell King (Oracle)
2025-10-27 12:50 ` Andrew Lunn
2025-10-27 14:50 ` Oleksij Rempel
2025-11-12 12:34 ` Russell King (Oracle)
2025-11-12 12:41 ` Kieran Bingham
2025-11-12 12:56 ` Russell King (Oracle)
2025-11-13 1:17 ` Laurent Pinchart
2025-11-12 21:32 ` Laurent Pinchart
2025-10-27 9:07 ` Russell King (Oracle)
2025-10-27 9:33 ` Laurent Pinchart
2025-10-27 9:45 ` Russell King (Oracle)
2025-10-27 9:55 ` Laurent Pinchart
2025-10-27 13:33 ` Russell King (Oracle)
2025-10-27 15:13 ` Russell King (Oracle)
2025-10-27 19:52 ` Andrew Lunn
2025-10-27 23:46 ` Laurent Pinchart
2025-10-28 0:57 ` Russell King (Oracle)
2025-10-28 7:18 ` Laurent Pinchart
2025-11-11 23:54 ` Laurent Pinchart
2025-11-12 12:03 ` Russell King (Oracle)
2025-11-12 22:25 ` Laurent Pinchart
2025-11-13 1:06 ` Laurent Pinchart
2025-11-13 10:59 ` Russell King (Oracle)
2025-11-14 22:26 ` Laurent Pinchart
2025-11-18 1:50 ` Wei Fang
2025-11-22 7:22 ` Laurent Pinchart
2025-11-22 9:57 ` Russell King (Oracle)
2025-11-23 5:38 ` Laurent Pinchart
2025-11-23 8:52 ` Russell King (Oracle)
2025-11-23 15:23 ` Laurent Pinchart
2025-11-23 17:11 ` Russell King (Oracle)
2025-11-24 0:12 ` Laurent Pinchart
2025-11-24 5:44 ` Oleksij Rempel
2025-11-24 8:43 ` Russell King (Oracle)
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