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Thu, 06 Nov 2025 18:44:03 -0800 (PST) Date: Thu, 6 Nov 2025 23:43:57 -0300 From: Geraldo Nascimento To: Shawn Lin Cc: Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Conor Dooley , Johan Jonker , linux-rockchip@lists.infradead.org Subject: Re: [PATCH] arm64: dts: rockchip: align bindings to PCIe spec Message-ID: References: <4b5ffcccfef2a61838aa563521672a171acb27b2.1762321976.git.geraldogabriel@gmail.com> <67b605b0-7046-448a-bc9b-d3ac56333809@rock-chips.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <67b605b0-7046-448a-bc9b-d3ac56333809@rock-chips.com> On Wed, Nov 05, 2025 at 04:56:36PM +0800, Shawn Lin wrote: > 在 2025/11/05 星期三 16:18, Geraldo Nascimento 写道: > > Hi Shawn, glad to hear from you. > > > > Perhaps the following change is better? It resolves the issue > > without the added complication of open drain. After you questioned > > if open drain is actually part of the spec, I remembered that > > GPIO_OPEN_DRAIN is actually (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) > > so I decided to test with just GPIO_SINGLE_ENDED and it works. Shawn, I quote from the PCIe Mini Card Electromechanical Specification Rev 1.2 "3.4.1. Logic Signal Requirements The 3.3V card logic levels for single-ended digital signals (WAKE#, CLKREQ#, PERST#, and W_DISABLE#) are given in Table 3-7. [...]" So while you are correct that PERST# is most definitely not Open Drain, there's evidence on the spec that defines this signal as Single-Ended. Thanks, Geraldo Nascimento