[PATCH v3 0/5] Add reset controllers for other TH1520 subsystems

[PATCH v3 0/5] Add reset controllers for other TH1520 subsystems

[Yao Zi]

TH1520 SoC is split into several subsystems, and each of them comes with
distinct reset controllers. We've already had the one for VO subsystem
documented as "thead,th1520-reset" and supported, and this series adds
support for others, including AO, VI, MISC, AP, DSP and VO.

For TH1520_RESET_ID_{NPU,WDT0,WDT1}, these're reset signals that have
been introduced along with support for the VO reset controller. However,
registers in control of these resets don't stay in the VO reset region,
instead they're AP-subsystem resets, thus the original ABI is
problematic. I remove them in PATCH 1 and reintroduce them in PATCH 2.

Note the reset controller for AO subsystem is marked as "reserved" in
devicetree since AON firmware may make use of it and access in Linux
side may cause races.

This series is based on next-20251013, thanks for your time and review.

Changed from v2
- Collect review tags
- Fix duplicated dt-binding IDs for DSP-subsystem resets
- Link to v2: https://lore.kernel.org/all/20250915095331.53350-1-ziyao@disroot.org/

Changed from v1
- Make a separate patch for the ABI-breaking change of
  TH1520_RESET_ID_{NPU,WDT0,WDT1}
- Fix the duplicated dt-binding IDs
- Sort compatibles/reset-signal definitions in alphabetical order in
  the driver
- Sort dt-binding IDs in alphabetical order by subsystem names
- Link to v1: https://lore.kernel.org/all/20250901042320.22865-1-ziyao@disroot.org/

Yao Zi (5):
  dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets
  dt-bindings: reset: thead,th1520-reset: Add controllers for more
    subsys
  reset: th1520: Prepare for supporting multiple controllers
  reset: th1520: Support reset controllers in more subsystems
  riscv: dts: thead: Add reset controllers of more subsystems for TH1520

 .../bindings/reset/thead,th1520-reset.yaml    |   8 +-
 arch/riscv/boot/dts/thead/th1520.dtsi         |  37 +
 drivers/reset/reset-th1520.c                  | 835 +++++++++++++++++-
 .../dt-bindings/reset/thead,th1520-reset.h    | 219 ++++-
 4 files changed, 1083 insertions(+), 16 deletions(-)

-- 
2.50.1

[PATCH v3 1/5] dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets

[Yao Zi]

Registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} belong to AP
reset controller, not the VO one which is documented as
"thead,th1520-reset" and is the only reset controller supported for
TH1520 for now.

Let's remove the IDs, leaving them to be implemented by AP-subsystem
reset controller in the future.

Fixes: 30e7573babdc ("dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
 include/dt-bindings/reset/thead,th1520-reset.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h
index ee799286c175..e51d6314d131 100644
--- a/include/dt-bindings/reset/thead,th1520-reset.h
+++ b/include/dt-bindings/reset/thead,th1520-reset.h
@@ -9,9 +9,6 @@
 
 #define TH1520_RESET_ID_GPU		0
 #define TH1520_RESET_ID_GPU_CLKGEN	1
-#define TH1520_RESET_ID_NPU		2
-#define TH1520_RESET_ID_WDT0		3
-#define TH1520_RESET_ID_WDT1		4
 #define TH1520_RESET_ID_DPU_AHB		5
 #define TH1520_RESET_ID_DPU_AXI		6
 #define TH1520_RESET_ID_DPU_CORE	7
-- 
2.50.1

Re: [PATCH v3 1/5] dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets

[Guo Ren]

On Tue, Oct 14, 2025 at 9:11 PM Yao Zi <ziyao@disroot.org> wrote:
>
> Registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} belong to AP
> reset controller, not the VO one which is documented as
> "thead,th1520-reset" and is the only reset controller supported for
> TH1520 for now.
>
> Let's remove the IDs, leaving them to be implemented by AP-subsystem
> reset controller in the future.

LGTM.

Acked-by: Guo Ren <guoren@kernel.org>

>
> Fixes: 30e7573babdc ("dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller")
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> ---
>  include/dt-bindings/reset/thead,th1520-reset.h | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h
> index ee799286c175..e51d6314d131 100644
> --- a/include/dt-bindings/reset/thead,th1520-reset.h
> +++ b/include/dt-bindings/reset/thead,th1520-reset.h
> @@ -9,9 +9,6 @@
>
>  #define TH1520_RESET_ID_GPU            0
>  #define TH1520_RESET_ID_GPU_CLKGEN     1
> -#define TH1520_RESET_ID_NPU            2
> -#define TH1520_RESET_ID_WDT0           3
> -#define TH1520_RESET_ID_WDT1           4
>  #define TH1520_RESET_ID_DPU_AHB                5
>  #define TH1520_RESET_ID_DPU_AXI                6
>  #define TH1520_RESET_ID_DPU_CORE       7
> --
> 2.50.1
>


-- 
Best Regards
 Guo Ren

Re: [PATCH v3 1/5] dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets

[Drew Fustini]

On Tue, Oct 14, 2025 at 01:10:28PM +0000, Yao Zi wrote:
> Registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} belong to AP
> reset controller, not the VO one which is documented as
> "thead,th1520-reset" and is the only reset controller supported for
> TH1520 for now.
> 
> Let's remove the IDs, leaving them to be implemented by AP-subsystem
> reset controller in the future.
> 
> Fixes: 30e7573babdc ("dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller")
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> ---
>  include/dt-bindings/reset/thead,th1520-reset.h | 3 ---
>  1 file changed, 3 deletions(-)

Reviewed-by: Drew Fustini <fustini@kernel.org>

[PATCH v3 2/5] dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys

[Yao Zi]

TH1520 SoC is divided into several subsystems, most of them have
distinct reset controllers. Let's document reset controllers other than
the one for VO subsystem and IDs for their reset signals.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
 .../bindings/reset/thead,th1520-reset.yaml    |   8 +-
 .../dt-bindings/reset/thead,th1520-reset.h    | 216 ++++++++++++++++++
 2 files changed, 223 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
index f2e91d0add7a..7b5053c177fe 100644
--- a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
@@ -16,7 +16,13 @@ maintainers:
 properties:
   compatible:
     enum:
-      - thead,th1520-reset
+      - thead,th1520-reset # Reset controller for VO subsystem
+      - thead,th1520-reset-ao
+      - thead,th1520-reset-ap
+      - thead,th1520-reset-dsp
+      - thead,th1520-reset-misc
+      - thead,th1520-reset-vi
+      - thead,th1520-reset-vp
 
   reg:
     maxItems: 1
diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h
index e51d6314d131..ba6805b6b12a 100644
--- a/include/dt-bindings/reset/thead,th1520-reset.h
+++ b/include/dt-bindings/reset/thead,th1520-reset.h
@@ -7,6 +7,200 @@
 #ifndef _DT_BINDINGS_TH1520_RESET_H
 #define _DT_BINDINGS_TH1520_RESET_H
 
+/* AO Subsystem */
+#define TH1520_RESET_ID_SYSTEM		0
+#define TH1520_RESET_ID_RTC_APB		1
+#define TH1520_RESET_ID_RTC_REF		2
+#define TH1520_RESET_ID_AOGPIO_DB	3
+#define TH1520_RESET_ID_AOGPIO_APB	4
+#define TH1520_RESET_ID_AOI2C_APB	5
+#define TH1520_RESET_ID_PVT_APB		6
+#define TH1520_RESET_ID_E902_CORE	7
+#define TH1520_RESET_ID_E902_HAD	8
+#define TH1520_RESET_ID_AOTIMER_APB	9
+#define TH1520_RESET_ID_AOTIMER_CORE	10
+#define TH1520_RESET_ID_AOWDT_APB	11
+#define TH1520_RESET_ID_APSYS		12
+#define TH1520_RESET_ID_NPUSYS		13
+#define TH1520_RESET_ID_DDRSYS		14
+#define TH1520_RESET_ID_AXI_AP2CP	15
+#define TH1520_RESET_ID_AXI_CP2AP	16
+#define TH1520_RESET_ID_AXI_CP2SRAM	17
+#define TH1520_RESET_ID_AUDSYS_CORE	18
+#define TH1520_RESET_ID_AUDSYS_IOPMP	19
+#define TH1520_RESET_ID_AUDSYS		20
+#define TH1520_RESET_ID_DSP0		21
+#define TH1520_RESET_ID_DSP1		22
+#define TH1520_RESET_ID_GPU_MODULE	23
+#define TH1520_RESET_ID_VDEC		24
+#define TH1520_RESET_ID_VENC		25
+#define TH1520_RESET_ID_ADC_APB		26
+#define TH1520_RESET_ID_AUDGPIO_DB	27
+#define TH1520_RESET_ID_AUDGPIO_APB	28
+#define TH1520_RESET_ID_AOUART_IF	29
+#define TH1520_RESET_ID_AOUART_APB	30
+#define TH1520_RESET_ID_SRAM_AXI_P0	31
+#define TH1520_RESET_ID_SRAM_AXI_P1	32
+#define TH1520_RESET_ID_SRAM_AXI_P2	33
+#define TH1520_RESET_ID_SRAM_AXI_P3	34
+#define TH1520_RESET_ID_SRAM_AXI_P4	35
+#define TH1520_RESET_ID_SRAM_AXI_CORE	36
+#define TH1520_RESET_ID_SE		37
+
+/* AP Subsystem */
+#define TH1520_RESET_ID_BROM			0
+#define TH1520_RESET_ID_C910_TOP		1
+#define TH1520_RESET_ID_NPU			2
+#define TH1520_RESET_ID_WDT0			3
+#define TH1520_RESET_ID_WDT1			4
+#define TH1520_RESET_ID_C910_C0			5
+#define TH1520_RESET_ID_C910_C1			6
+#define TH1520_RESET_ID_C910_C2			7
+#define TH1520_RESET_ID_C910_C3			8
+#define TH1520_RESET_ID_CHIP_DBG_CORE		9
+#define TH1520_RESET_ID_CHIP_DBG_AXI		10
+#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI	11
+#define TH1520_RESET_ID_AXI4_CPUSYS2_APB	12
+#define TH1520_RESET_ID_X2H_CPUSYS		13
+#define TH1520_RESET_ID_AHB2_CPUSYS		14
+#define TH1520_RESET_ID_APB3_CPUSYS		15
+#define TH1520_RESET_ID_MBOX0_APB		16
+#define TH1520_RESET_ID_MBOX1_APB		17
+#define TH1520_RESET_ID_MBOX2_APB		18
+#define TH1520_RESET_ID_MBOX3_APB		19
+#define TH1520_RESET_ID_TIMER0_APB		20
+#define TH1520_RESET_ID_TIMER0_CORE		21
+#define TH1520_RESET_ID_TIMER1_APB		22
+#define TH1520_RESET_ID_TIMER1_CORE		23
+#define TH1520_RESET_ID_PERISYS_AHB		24
+#define TH1520_RESET_ID_PERISYS_APB1		25
+#define TH1520_RESET_ID_PERISYS_APB2		26
+#define TH1520_RESET_ID_GMAC0_APB		27
+#define TH1520_RESET_ID_GMAC0_AHB		28
+#define TH1520_RESET_ID_GMAC0_CLKGEN		29
+#define TH1520_RESET_ID_GMAC0_AXI		30
+#define TH1520_RESET_ID_UART0_APB		31
+#define TH1520_RESET_ID_UART0_IF		32
+#define TH1520_RESET_ID_UART1_APB		33
+#define TH1520_RESET_ID_UART1_IF		34
+#define TH1520_RESET_ID_UART2_APB		35
+#define TH1520_RESET_ID_UART2_IF		36
+#define TH1520_RESET_ID_UART3_APB		37
+#define TH1520_RESET_ID_UART3_IF		38
+#define TH1520_RESET_ID_UART4_APB		39
+#define TH1520_RESET_ID_UART4_IF		40
+#define TH1520_RESET_ID_UART5_APB		41
+#define TH1520_RESET_ID_UART5_IF		42
+#define TH1520_RESET_ID_QSPI0_IF		43
+#define TH1520_RESET_ID_QSPI0_APB		44
+#define TH1520_RESET_ID_QSPI1_IF		45
+#define TH1520_RESET_ID_QSPI1_APB		46
+#define TH1520_RESET_ID_SPI_IF			47
+#define TH1520_RESET_ID_SPI_APB			48
+#define TH1520_RESET_ID_I2C0_APB		49
+#define TH1520_RESET_ID_I2C0_CORE		50
+#define TH1520_RESET_ID_I2C1_APB		51
+#define TH1520_RESET_ID_I2C1_CORE		52
+#define TH1520_RESET_ID_I2C2_APB		53
+#define TH1520_RESET_ID_I2C2_CORE		54
+#define TH1520_RESET_ID_I2C3_APB		55
+#define TH1520_RESET_ID_I2C3_CORE		56
+#define TH1520_RESET_ID_I2C4_APB		57
+#define TH1520_RESET_ID_I2C4_CORE		58
+#define TH1520_RESET_ID_I2C5_APB		59
+#define TH1520_RESET_ID_I2C5_CORE		60
+#define TH1520_RESET_ID_GPIO0_DB		61
+#define TH1520_RESET_ID_GPIO0_APB		62
+#define TH1520_RESET_ID_GPIO1_DB		63
+#define TH1520_RESET_ID_GPIO1_APB		64
+#define TH1520_RESET_ID_GPIO2_DB		65
+#define TH1520_RESET_ID_GPIO2_APB		66
+#define TH1520_RESET_ID_PWM_COUNTER		67
+#define TH1520_RESET_ID_PWM_APB			68
+#define TH1520_RESET_ID_PADCTRL0_APB		69
+#define TH1520_RESET_ID_CPU2PERI_X2H		70
+#define TH1520_RESET_ID_CPU2AON_X2H		71
+#define TH1520_RESET_ID_AON2CPU_A2X		72
+#define TH1520_RESET_ID_NPUSYS_AXI		73
+#define TH1520_RESET_ID_NPUSYS_AXI_APB		74
+#define TH1520_RESET_ID_CPU2VP_X2P		75
+#define TH1520_RESET_ID_CPU2VI_X2H		76
+#define TH1520_RESET_ID_BMU_AXI			77
+#define TH1520_RESET_ID_BMU_APB			78
+#define TH1520_RESET_ID_DMAC_CPUSYS_AXI		79
+#define TH1520_RESET_ID_DMAC_CPUSYS_AHB		80
+#define TH1520_RESET_ID_SPINLOCK		81
+#define TH1520_RESET_ID_CFG2TEE			82
+#define TH1520_RESET_ID_DSMART			83
+#define TH1520_RESET_ID_GPIO3_DB		84
+#define TH1520_RESET_ID_GPIO3_APB		85
+#define TH1520_RESET_ID_PERI_I2S		86
+#define TH1520_RESET_ID_PERI_APB3		87
+#define TH1520_RESET_ID_PERI2PERI1_APB		88
+#define TH1520_RESET_ID_VPSYS_APB		89
+#define TH1520_RESET_ID_PERISYS_APB4		90
+#define TH1520_RESET_ID_GMAC1_APB		91
+#define TH1520_RESET_ID_GMAC1_AHB		92
+#define TH1520_RESET_ID_GMAC1_CLKGEN		93
+#define TH1520_RESET_ID_GMAC1_AXI		94
+#define TH1520_RESET_ID_GMAC_AXI		95
+#define TH1520_RESET_ID_GMAC_AXI_APB		96
+#define TH1520_RESET_ID_PADCTRL1_APB		97
+#define TH1520_RESET_ID_VOSYS_AXI		98
+#define TH1520_RESET_ID_VOSYS_AXI_APB		99
+#define TH1520_RESET_ID_VOSYS_AXI_X2X		100
+#define TH1520_RESET_ID_MISC2VP_X2X		101
+#define TH1520_RESET_ID_DSPSYS			102
+#define TH1520_RESET_ID_VISYS			103
+#define TH1520_RESET_ID_VOSYS			104
+#define TH1520_RESET_ID_VPSYS			105
+
+/* DSP Subsystem */
+#define TH1520_RESET_ID_X2X_DSP1	0
+#define TH1520_RESET_ID_X2X_DSP0	1
+#define TH1520_RESET_ID_X2X_SLAVE_DSP1	2
+#define TH1520_RESET_ID_X2X_SLAVE_DSP0	3
+#define TH1520_RESET_ID_DSP0_CORE	4
+#define TH1520_RESET_ID_DSP0_DEBUG	5
+#define TH1520_RESET_ID_DSP0_APB	6
+#define TH1520_RESET_ID_DSP1_CORE	7
+#define TH1520_RESET_ID_DSP1_DEBUG	8
+#define TH1520_RESET_ID_DSP1_APB	9
+#define TH1520_RESET_ID_DSPSYS_APB	10
+#define TH1520_RESET_ID_AXI4_DSPSYS_SLV	11
+#define TH1520_RESET_ID_AXI4_DSPSYS	12
+#define TH1520_RESET_ID_AXI4_DSP_RS	13
+
+/* MISC Subsystem */
+#define TH1520_RESET_ID_EMMC_SDIO_CLKGEN	0
+#define TH1520_RESET_ID_EMMC			1
+#define TH1520_RESET_ID_MISCSYS_AXI		2
+#define TH1520_RESET_ID_MISCSYS_AXI_APB		3
+#define TH1520_RESET_ID_SDIO0			4
+#define TH1520_RESET_ID_SDIO1			5
+#define TH1520_RESET_ID_USB3_APB		6
+#define TH1520_RESET_ID_USB3_PHY		7
+#define TH1520_RESET_ID_USB3_VCC		8
+
+/* VI Subsystem */
+#define TH1520_RESET_ID_ISP0		0
+#define TH1520_RESET_ID_ISP1		1
+#define TH1520_RESET_ID_CSI0_APB	2
+#define TH1520_RESET_ID_CSI1_APB	3
+#define TH1520_RESET_ID_CSI2_APB	4
+#define TH1520_RESET_ID_MIPI_FIFO	5
+#define TH1520_RESET_ID_ISP_VENC_APB	6
+#define TH1520_RESET_ID_VIPRE_APB	7
+#define TH1520_RESET_ID_VIPRE_AXI	8
+#define TH1520_RESET_ID_DW200_APB	9
+#define TH1520_RESET_ID_VISYS3_AXI	10
+#define TH1520_RESET_ID_VISYS2_AXI	11
+#define TH1520_RESET_ID_VISYS1_AXI	12
+#define TH1520_RESET_ID_VISYS_AXI	13
+#define TH1520_RESET_ID_VISYS_APB	14
+#define TH1520_RESET_ID_ISP_VENC_AXI	15
+
+/* VO Subsystem */
 #define TH1520_RESET_ID_GPU		0
 #define TH1520_RESET_ID_GPU_CLKGEN	1
 #define TH1520_RESET_ID_DPU_AHB		5
@@ -16,5 +210,27 @@
 #define TH1520_RESET_ID_DSI1_APB	9
 #define TH1520_RESET_ID_HDMI		10
 #define TH1520_RESET_ID_HDMI_APB	11
+#define TH1520_RESET_ID_VOAXI		12
+#define TH1520_RESET_ID_VOAXI_APB	13
+#define TH1520_RESET_ID_X2H_DPU_AXI	14
+#define TH1520_RESET_ID_X2H_DPU_AHB	15
+#define TH1520_RESET_ID_X2H_DPU1_AXI	16
+#define TH1520_RESET_ID_X2H_DPU1_AHB	17
+
+/* VP Subsystem */
+#define TH1520_RESET_ID_VPSYS_AXI_APB	0
+#define TH1520_RESET_ID_VPSYS_AXI	1
+#define TH1520_RESET_ID_FCE_APB		2
+#define TH1520_RESET_ID_FCE_CORE	3
+#define TH1520_RESET_ID_FCE_X2X_MASTER	4
+#define TH1520_RESET_ID_FCE_X2X_SLAVE	5
+#define TH1520_RESET_ID_G2D_APB		6
+#define TH1520_RESET_ID_G2D_ACLK	7
+#define TH1520_RESET_ID_G2D_CORE	8
+#define TH1520_RESET_ID_VDEC_APB	9
+#define TH1520_RESET_ID_VDEC_ACLK	10
+#define TH1520_RESET_ID_VDEC_CORE	11
+#define TH1520_RESET_ID_VENC_APB	12
+#define TH1520_RESET_ID_VENC_CORE	13
 
 #endif /* _DT_BINDINGS_TH1520_RESET_H */
-- 
2.50.1

Re: [PATCH v3 2/5] dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys

[Guo Ren]

On Tue, Oct 14, 2025 at 9:11 PM Yao Zi <ziyao@disroot.org> wrote:
>
> TH1520 SoC is divided into several subsystems, most of them have
> distinct reset controllers. Let's document reset controllers other than
> the one for VO subsystem and IDs for their reset signals.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> ---
>  .../bindings/reset/thead,th1520-reset.yaml    |   8 +-
>  .../dt-bindings/reset/thead,th1520-reset.h    | 216 ++++++++++++++++++
>  2 files changed, 223 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
> index f2e91d0add7a..7b5053c177fe 100644
> --- a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
> @@ -16,7 +16,13 @@ maintainers:
>  properties:
>    compatible:
>      enum:
> -      - thead,th1520-reset
> +      - thead,th1520-reset # Reset controller for VO subsystem
> +      - thead,th1520-reset-ao
> +      - thead,th1520-reset-ap
> +      - thead,th1520-reset-dsp
> +      - thead,th1520-reset-misc
> +      - thead,th1520-reset-vi
> +      - thead,th1520-reset-vp
>
>    reg:
>      maxItems: 1
> diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h
> index e51d6314d131..ba6805b6b12a 100644
> --- a/include/dt-bindings/reset/thead,th1520-reset.h
> +++ b/include/dt-bindings/reset/thead,th1520-reset.h
> @@ -7,6 +7,200 @@
>  #ifndef _DT_BINDINGS_TH1520_RESET_H
>  #define _DT_BINDINGS_TH1520_RESET_H
>
> +/* AO Subsystem */
> +#define TH1520_RESET_ID_SYSTEM         0
> +#define TH1520_RESET_ID_RTC_APB                1
> +#define TH1520_RESET_ID_RTC_REF                2
> +#define TH1520_RESET_ID_AOGPIO_DB      3
> +#define TH1520_RESET_ID_AOGPIO_APB     4
> +#define TH1520_RESET_ID_AOI2C_APB      5
> +#define TH1520_RESET_ID_PVT_APB                6
> +#define TH1520_RESET_ID_E902_CORE      7
> +#define TH1520_RESET_ID_E902_HAD       8
> +#define TH1520_RESET_ID_AOTIMER_APB    9
> +#define TH1520_RESET_ID_AOTIMER_CORE   10
> +#define TH1520_RESET_ID_AOWDT_APB      11
> +#define TH1520_RESET_ID_APSYS          12
> +#define TH1520_RESET_ID_NPUSYS         13
> +#define TH1520_RESET_ID_DDRSYS         14
> +#define TH1520_RESET_ID_AXI_AP2CP      15
> +#define TH1520_RESET_ID_AXI_CP2AP      16
> +#define TH1520_RESET_ID_AXI_CP2SRAM    17
> +#define TH1520_RESET_ID_AUDSYS_CORE    18
> +#define TH1520_RESET_ID_AUDSYS_IOPMP   19
> +#define TH1520_RESET_ID_AUDSYS         20
> +#define TH1520_RESET_ID_DSP0           21
> +#define TH1520_RESET_ID_DSP1           22
> +#define TH1520_RESET_ID_GPU_MODULE     23
> +#define TH1520_RESET_ID_VDEC           24
> +#define TH1520_RESET_ID_VENC           25
> +#define TH1520_RESET_ID_ADC_APB                26
> +#define TH1520_RESET_ID_AUDGPIO_DB     27
> +#define TH1520_RESET_ID_AUDGPIO_APB    28
> +#define TH1520_RESET_ID_AOUART_IF      29
> +#define TH1520_RESET_ID_AOUART_APB     30
> +#define TH1520_RESET_ID_SRAM_AXI_P0    31
> +#define TH1520_RESET_ID_SRAM_AXI_P1    32
> +#define TH1520_RESET_ID_SRAM_AXI_P2    33
> +#define TH1520_RESET_ID_SRAM_AXI_P3    34
> +#define TH1520_RESET_ID_SRAM_AXI_P4    35
> +#define TH1520_RESET_ID_SRAM_AXI_CORE  36
> +#define TH1520_RESET_ID_SE             37
> +
> +/* AP Subsystem */
> +#define TH1520_RESET_ID_BROM                   0
> +#define TH1520_RESET_ID_C910_TOP               1
> +#define TH1520_RESET_ID_NPU                    2
> +#define TH1520_RESET_ID_WDT0                   3
> +#define TH1520_RESET_ID_WDT1                   4
> +#define TH1520_RESET_ID_C910_C0                        5
> +#define TH1520_RESET_ID_C910_C1                        6
> +#define TH1520_RESET_ID_C910_C2                        7
> +#define TH1520_RESET_ID_C910_C3                        8
> +#define TH1520_RESET_ID_CHIP_DBG_CORE          9
> +#define TH1520_RESET_ID_CHIP_DBG_AXI           10
> +#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI       11
> +#define TH1520_RESET_ID_AXI4_CPUSYS2_APB       12
> +#define TH1520_RESET_ID_X2H_CPUSYS             13
> +#define TH1520_RESET_ID_AHB2_CPUSYS            14
> +#define TH1520_RESET_ID_APB3_CPUSYS            15
> +#define TH1520_RESET_ID_MBOX0_APB              16
> +#define TH1520_RESET_ID_MBOX1_APB              17
> +#define TH1520_RESET_ID_MBOX2_APB              18
> +#define TH1520_RESET_ID_MBOX3_APB              19
> +#define TH1520_RESET_ID_TIMER0_APB             20
> +#define TH1520_RESET_ID_TIMER0_CORE            21
> +#define TH1520_RESET_ID_TIMER1_APB             22
> +#define TH1520_RESET_ID_TIMER1_CORE            23
> +#define TH1520_RESET_ID_PERISYS_AHB            24
> +#define TH1520_RESET_ID_PERISYS_APB1           25
> +#define TH1520_RESET_ID_PERISYS_APB2           26
> +#define TH1520_RESET_ID_GMAC0_APB              27
> +#define TH1520_RESET_ID_GMAC0_AHB              28
> +#define TH1520_RESET_ID_GMAC0_CLKGEN           29
> +#define TH1520_RESET_ID_GMAC0_AXI              30
> +#define TH1520_RESET_ID_UART0_APB              31
> +#define TH1520_RESET_ID_UART0_IF               32
> +#define TH1520_RESET_ID_UART1_APB              33
> +#define TH1520_RESET_ID_UART1_IF               34
> +#define TH1520_RESET_ID_UART2_APB              35
> +#define TH1520_RESET_ID_UART2_IF               36
> +#define TH1520_RESET_ID_UART3_APB              37
> +#define TH1520_RESET_ID_UART3_IF               38
> +#define TH1520_RESET_ID_UART4_APB              39
> +#define TH1520_RESET_ID_UART4_IF               40
> +#define TH1520_RESET_ID_UART5_APB              41
> +#define TH1520_RESET_ID_UART5_IF               42
> +#define TH1520_RESET_ID_QSPI0_IF               43
> +#define TH1520_RESET_ID_QSPI0_APB              44
> +#define TH1520_RESET_ID_QSPI1_IF               45
> +#define TH1520_RESET_ID_QSPI1_APB              46
> +#define TH1520_RESET_ID_SPI_IF                 47
> +#define TH1520_RESET_ID_SPI_APB                        48
> +#define TH1520_RESET_ID_I2C0_APB               49
> +#define TH1520_RESET_ID_I2C0_CORE              50
> +#define TH1520_RESET_ID_I2C1_APB               51
> +#define TH1520_RESET_ID_I2C1_CORE              52
> +#define TH1520_RESET_ID_I2C2_APB               53
> +#define TH1520_RESET_ID_I2C2_CORE              54
> +#define TH1520_RESET_ID_I2C3_APB               55
> +#define TH1520_RESET_ID_I2C3_CORE              56
> +#define TH1520_RESET_ID_I2C4_APB               57
> +#define TH1520_RESET_ID_I2C4_CORE              58
> +#define TH1520_RESET_ID_I2C5_APB               59
> +#define TH1520_RESET_ID_I2C5_CORE              60
> +#define TH1520_RESET_ID_GPIO0_DB               61
> +#define TH1520_RESET_ID_GPIO0_APB              62
> +#define TH1520_RESET_ID_GPIO1_DB               63
> +#define TH1520_RESET_ID_GPIO1_APB              64
> +#define TH1520_RESET_ID_GPIO2_DB               65
> +#define TH1520_RESET_ID_GPIO2_APB              66
> +#define TH1520_RESET_ID_PWM_COUNTER            67
> +#define TH1520_RESET_ID_PWM_APB                        68
> +#define TH1520_RESET_ID_PADCTRL0_APB           69
> +#define TH1520_RESET_ID_CPU2PERI_X2H           70
> +#define TH1520_RESET_ID_CPU2AON_X2H            71
> +#define TH1520_RESET_ID_AON2CPU_A2X            72
> +#define TH1520_RESET_ID_NPUSYS_AXI             73
> +#define TH1520_RESET_ID_NPUSYS_AXI_APB         74
> +#define TH1520_RESET_ID_CPU2VP_X2P             75
> +#define TH1520_RESET_ID_CPU2VI_X2H             76
> +#define TH1520_RESET_ID_BMU_AXI                        77
> +#define TH1520_RESET_ID_BMU_APB                        78
> +#define TH1520_RESET_ID_DMAC_CPUSYS_AXI                79
> +#define TH1520_RESET_ID_DMAC_CPUSYS_AHB                80
> +#define TH1520_RESET_ID_SPINLOCK               81
> +#define TH1520_RESET_ID_CFG2TEE                        82
> +#define TH1520_RESET_ID_DSMART                 83
> +#define TH1520_RESET_ID_GPIO3_DB               84
> +#define TH1520_RESET_ID_GPIO3_APB              85
> +#define TH1520_RESET_ID_PERI_I2S               86
> +#define TH1520_RESET_ID_PERI_APB3              87
> +#define TH1520_RESET_ID_PERI2PERI1_APB         88
> +#define TH1520_RESET_ID_VPSYS_APB              89
> +#define TH1520_RESET_ID_PERISYS_APB4           90
> +#define TH1520_RESET_ID_GMAC1_APB              91
> +#define TH1520_RESET_ID_GMAC1_AHB              92
> +#define TH1520_RESET_ID_GMAC1_CLKGEN           93
> +#define TH1520_RESET_ID_GMAC1_AXI              94
> +#define TH1520_RESET_ID_GMAC_AXI               95
> +#define TH1520_RESET_ID_GMAC_AXI_APB           96
> +#define TH1520_RESET_ID_PADCTRL1_APB           97
> +#define TH1520_RESET_ID_VOSYS_AXI              98
> +#define TH1520_RESET_ID_VOSYS_AXI_APB          99
> +#define TH1520_RESET_ID_VOSYS_AXI_X2X          100
> +#define TH1520_RESET_ID_MISC2VP_X2X            101
> +#define TH1520_RESET_ID_DSPSYS                 102
> +#define TH1520_RESET_ID_VISYS                  103
> +#define TH1520_RESET_ID_VOSYS                  104
> +#define TH1520_RESET_ID_VPSYS                  105
> +
> +/* DSP Subsystem */
> +#define TH1520_RESET_ID_X2X_DSP1       0
> +#define TH1520_RESET_ID_X2X_DSP0       1
> +#define TH1520_RESET_ID_X2X_SLAVE_DSP1 2
> +#define TH1520_RESET_ID_X2X_SLAVE_DSP0 3
> +#define TH1520_RESET_ID_DSP0_CORE      4
> +#define TH1520_RESET_ID_DSP0_DEBUG     5
> +#define TH1520_RESET_ID_DSP0_APB       6
> +#define TH1520_RESET_ID_DSP1_CORE      7
> +#define TH1520_RESET_ID_DSP1_DEBUG     8
> +#define TH1520_RESET_ID_DSP1_APB       9
> +#define TH1520_RESET_ID_DSPSYS_APB     10
> +#define TH1520_RESET_ID_AXI4_DSPSYS_SLV        11
> +#define TH1520_RESET_ID_AXI4_DSPSYS    12
> +#define TH1520_RESET_ID_AXI4_DSP_RS    13
> +
> +/* MISC Subsystem */
> +#define TH1520_RESET_ID_EMMC_SDIO_CLKGEN       0
> +#define TH1520_RESET_ID_EMMC                   1
> +#define TH1520_RESET_ID_MISCSYS_AXI            2
> +#define TH1520_RESET_ID_MISCSYS_AXI_APB                3
> +#define TH1520_RESET_ID_SDIO0                  4
> +#define TH1520_RESET_ID_SDIO1                  5
> +#define TH1520_RESET_ID_USB3_APB               6
> +#define TH1520_RESET_ID_USB3_PHY               7
> +#define TH1520_RESET_ID_USB3_VCC               8
> +
> +/* VI Subsystem */
> +#define TH1520_RESET_ID_ISP0           0
> +#define TH1520_RESET_ID_ISP1           1
> +#define TH1520_RESET_ID_CSI0_APB       2
> +#define TH1520_RESET_ID_CSI1_APB       3
> +#define TH1520_RESET_ID_CSI2_APB       4
> +#define TH1520_RESET_ID_MIPI_FIFO      5
> +#define TH1520_RESET_ID_ISP_VENC_APB   6
> +#define TH1520_RESET_ID_VIPRE_APB      7
> +#define TH1520_RESET_ID_VIPRE_AXI      8
> +#define TH1520_RESET_ID_DW200_APB      9
> +#define TH1520_RESET_ID_VISYS3_AXI     10
> +#define TH1520_RESET_ID_VISYS2_AXI     11
> +#define TH1520_RESET_ID_VISYS1_AXI     12
> +#define TH1520_RESET_ID_VISYS_AXI      13
> +#define TH1520_RESET_ID_VISYS_APB      14
> +#define TH1520_RESET_ID_ISP_VENC_AXI   15
> +
> +/* VO Subsystem */
>  #define TH1520_RESET_ID_GPU            0
>  #define TH1520_RESET_ID_GPU_CLKGEN     1
>  #define TH1520_RESET_ID_DPU_AHB                5
> @@ -16,5 +210,27 @@
>  #define TH1520_RESET_ID_DSI1_APB       9
>  #define TH1520_RESET_ID_HDMI           10
>  #define TH1520_RESET_ID_HDMI_APB       11
> +#define TH1520_RESET_ID_VOAXI          12
> +#define TH1520_RESET_ID_VOAXI_APB      13
> +#define TH1520_RESET_ID_X2H_DPU_AXI    14
> +#define TH1520_RESET_ID_X2H_DPU_AHB    15
> +#define TH1520_RESET_ID_X2H_DPU1_AXI   16
> +#define TH1520_RESET_ID_X2H_DPU1_AHB   17
> +
> +/* VP Subsystem */
> +#define TH1520_RESET_ID_VPSYS_AXI_APB  0
> +#define TH1520_RESET_ID_VPSYS_AXI      1
> +#define TH1520_RESET_ID_FCE_APB                2
> +#define TH1520_RESET_ID_FCE_CORE       3
> +#define TH1520_RESET_ID_FCE_X2X_MASTER 4
> +#define TH1520_RESET_ID_FCE_X2X_SLAVE  5
> +#define TH1520_RESET_ID_G2D_APB                6
> +#define TH1520_RESET_ID_G2D_ACLK       7
> +#define TH1520_RESET_ID_G2D_CORE       8
> +#define TH1520_RESET_ID_VDEC_APB       9
> +#define TH1520_RESET_ID_VDEC_ACLK      10
> +#define TH1520_RESET_ID_VDEC_CORE      11
> +#define TH1520_RESET_ID_VENC_APB       12
> +#define TH1520_RESET_ID_VENC_CORE      13
>
>  #endif /* _DT_BINDINGS_TH1520_RESET_H */
> --
> 2.50.1
>
Thanks for the work on the RESET module.

Acked-by: Guo Ren <guoren@kernel.org>

-- 
Best Regards
 Guo Ren

Re: [PATCH v3 2/5] dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys

[Drew Fustini]

On Tue, Oct 14, 2025 at 01:10:29PM +0000, Yao Zi wrote:
> TH1520 SoC is divided into several subsystems, most of them have
> distinct reset controllers. Let's document reset controllers other than
> the one for VO subsystem and IDs for their reset signals.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> ---
>  .../bindings/reset/thead,th1520-reset.yaml    |   8 +-
>  .../dt-bindings/reset/thead,th1520-reset.h    | 216 ++++++++++++++++++
>  2 files changed, 223 insertions(+), 1 deletion(-)

Reviewed-by: Drew Fustini <fustini@kernel.org>

[PATCH v3 3/5] reset: th1520: Prepare for supporting multiple controllers

[Yao Zi]

TH1520 SoC is divided into several subsystems, shipping distinct reset
controllers with similar control logic. Let's make reset signal mapping
a data structure specific to one compatible to prepare for introduction
of more reset controllers in the future.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 drivers/reset/reset-th1520.c | 42 +++++++++++++++++++++++++-----------
 1 file changed, 30 insertions(+), 12 deletions(-)

diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c
index 14d964a9c6b6..2b65a95ed021 100644
--- a/drivers/reset/reset-th1520.c
+++ b/drivers/reset/reset-th1520.c
@@ -29,14 +29,20 @@
 #define TH1520_HDMI_SW_MAIN_RST		BIT(0)
 #define TH1520_HDMI_SW_PRST		BIT(1)
 
+struct th1520_reset_map {
+	u32 bit;
+	u32 reg;
+};
+
 struct th1520_reset_priv {
 	struct reset_controller_dev rcdev;
 	struct regmap *map;
+	const struct th1520_reset_map *resets;
 };
 
-struct th1520_reset_map {
-	u32 bit;
-	u32 reg;
+struct th1520_reset_data {
+	const struct th1520_reset_map *resets;
+	size_t num;
 };
 
 static const struct th1520_reset_map th1520_resets[] = {
@@ -90,7 +96,7 @@ static int th1520_reset_assert(struct reset_controller_dev *rcdev,
 	struct th1520_reset_priv *priv = to_th1520_reset(rcdev);
 	const struct th1520_reset_map *reset;
 
-	reset = &th1520_resets[id];
+	reset = &priv->resets[id];
 
 	return regmap_update_bits(priv->map, reset->reg, reset->bit, 0);
 }
@@ -101,7 +107,7 @@ static int th1520_reset_deassert(struct reset_controller_dev *rcdev,
 	struct th1520_reset_priv *priv = to_th1520_reset(rcdev);
 	const struct th1520_reset_map *reset;
 
-	reset = &th1520_resets[id];
+	reset = &priv->resets[id];
 
 	return regmap_update_bits(priv->map, reset->reg, reset->bit,
 				  reset->bit);
@@ -120,11 +126,14 @@ static const struct regmap_config th1520_reset_regmap_config = {
 
 static int th1520_reset_probe(struct platform_device *pdev)
 {
+	const struct th1520_reset_data *data;
 	struct device *dev = &pdev->dev;
 	struct th1520_reset_priv *priv;
 	void __iomem *base;
 	int ret;
 
+	data = device_get_match_data(dev);
+
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
@@ -138,22 +147,31 @@ static int th1520_reset_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->map))
 		return PTR_ERR(priv->map);
 
-	/* Initialize GPU resets to asserted state */
-	ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG,
-				 TH1520_GPU_RST_CFG_MASK, 0);
-	if (ret)
-		return ret;
+	if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) {
+		/* Initialize GPU resets to asserted state */
+		ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG,
+					 TH1520_GPU_RST_CFG_MASK, 0);
+		if (ret)
+			return ret;
+	}
 
 	priv->rcdev.owner = THIS_MODULE;
-	priv->rcdev.nr_resets = ARRAY_SIZE(th1520_resets);
+	priv->rcdev.nr_resets = data->num;
 	priv->rcdev.ops = &th1520_reset_ops;
 	priv->rcdev.of_node = dev->of_node;
 
+	priv->resets = data->resets;
+
 	return devm_reset_controller_register(dev, &priv->rcdev);
 }
 
+static const struct th1520_reset_data th1520_reset_data = {
+	.resets = th1520_resets,
+	.num = ARRAY_SIZE(th1520_resets),
+};
+
 static const struct of_device_id th1520_reset_match[] = {
-	{ .compatible = "thead,th1520-reset" },
+	{ .compatible = "thead,th1520-reset", .data = &th1520_reset_data },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, th1520_reset_match);
-- 
2.50.1

Re: [PATCH v3 3/5] reset: th1520: Prepare for supporting multiple controllers

[Guo Ren]

Hi Yao,

On Tue, Oct 14, 2025 at 9:12 PM Yao Zi <ziyao@disroot.org> wrote:
>
> TH1520 SoC is divided into several subsystems, shipping distinct reset
> controllers with similar control logic. Let's make reset signal mapping
> a data structure specific to one compatible to prepare for introduction
> of more reset controllers in the future.
Move th1520_resets to .priv data makes sense, LGTM.

Acked-by: Guo Ren <guoren@kernel.org>

>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  drivers/reset/reset-th1520.c | 42 +++++++++++++++++++++++++-----------
>  1 file changed, 30 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c
> index 14d964a9c6b6..2b65a95ed021 100644
> --- a/drivers/reset/reset-th1520.c
> +++ b/drivers/reset/reset-th1520.c
> @@ -29,14 +29,20 @@
>  #define TH1520_HDMI_SW_MAIN_RST                BIT(0)
>  #define TH1520_HDMI_SW_PRST            BIT(1)
>
> +struct th1520_reset_map {
> +       u32 bit;
> +       u32 reg;
> +};
> +
>  struct th1520_reset_priv {
>         struct reset_controller_dev rcdev;
>         struct regmap *map;
> +       const struct th1520_reset_map *resets;
>  };
>
> -struct th1520_reset_map {
> -       u32 bit;
> -       u32 reg;
> +struct th1520_reset_data {
> +       const struct th1520_reset_map *resets;
> +       size_t num;
>  };
>
>  static const struct th1520_reset_map th1520_resets[] = {
> @@ -90,7 +96,7 @@ static int th1520_reset_assert(struct reset_controller_dev *rcdev,
>         struct th1520_reset_priv *priv = to_th1520_reset(rcdev);
>         const struct th1520_reset_map *reset;
>
> -       reset = &th1520_resets[id];
> +       reset = &priv->resets[id];
>
>         return regmap_update_bits(priv->map, reset->reg, reset->bit, 0);
>  }
> @@ -101,7 +107,7 @@ static int th1520_reset_deassert(struct reset_controller_dev *rcdev,
>         struct th1520_reset_priv *priv = to_th1520_reset(rcdev);
>         const struct th1520_reset_map *reset;
>
> -       reset = &th1520_resets[id];
> +       reset = &priv->resets[id];
>
>         return regmap_update_bits(priv->map, reset->reg, reset->bit,
>                                   reset->bit);
> @@ -120,11 +126,14 @@ static const struct regmap_config th1520_reset_regmap_config = {
>
>  static int th1520_reset_probe(struct platform_device *pdev)
>  {
> +       const struct th1520_reset_data *data;
>         struct device *dev = &pdev->dev;
>         struct th1520_reset_priv *priv;
>         void __iomem *base;
>         int ret;
>
> +       data = device_get_match_data(dev);
> +
>         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>         if (!priv)
>                 return -ENOMEM;
> @@ -138,22 +147,31 @@ static int th1520_reset_probe(struct platform_device *pdev)
>         if (IS_ERR(priv->map))
>                 return PTR_ERR(priv->map);
>
> -       /* Initialize GPU resets to asserted state */
> -       ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG,
> -                                TH1520_GPU_RST_CFG_MASK, 0);
> -       if (ret)
> -               return ret;
> +       if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) {
> +               /* Initialize GPU resets to asserted state */
> +               ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG,
> +                                        TH1520_GPU_RST_CFG_MASK, 0);
> +               if (ret)
> +                       return ret;
> +       }
>
>         priv->rcdev.owner = THIS_MODULE;
> -       priv->rcdev.nr_resets = ARRAY_SIZE(th1520_resets);
> +       priv->rcdev.nr_resets = data->num;
>         priv->rcdev.ops = &th1520_reset_ops;
>         priv->rcdev.of_node = dev->of_node;
>
> +       priv->resets = data->resets;
> +
>         return devm_reset_controller_register(dev, &priv->rcdev);
>  }
>
> +static const struct th1520_reset_data th1520_reset_data = {
> +       .resets = th1520_resets,
> +       .num = ARRAY_SIZE(th1520_resets),
> +};
> +
>  static const struct of_device_id th1520_reset_match[] = {
> -       { .compatible = "thead,th1520-reset" },
> +       { .compatible = "thead,th1520-reset", .data = &th1520_reset_data },
>         { /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, th1520_reset_match);
> --
> 2.50.1
>


-- 
Best Regards
 Guo Ren

Re: [PATCH v3 3/5] reset: th1520: Prepare for supporting multiple controllers

[Drew Fustini]

On Tue, Oct 14, 2025 at 01:10:30PM +0000, Yao Zi wrote:
> TH1520 SoC is divided into several subsystems, shipping distinct reset
> controllers with similar control logic. Let's make reset signal mapping
> a data structure specific to one compatible to prepare for introduction
> of more reset controllers in the future.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  drivers/reset/reset-th1520.c | 42 +++++++++++++++++++++++++-----------
>  1 file changed, 30 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c
> index 14d964a9c6b6..2b65a95ed021 100644
> --- a/drivers/reset/reset-th1520.c
> +++ b/drivers/reset/reset-th1520.c
[snip]
> @@ -138,22 +147,31 @@ static int th1520_reset_probe(struct platform_device *pdev)
>  	if (IS_ERR(priv->map))
>  		return PTR_ERR(priv->map);
>  
> -	/* Initialize GPU resets to asserted state */
> -	ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG,
> -				 TH1520_GPU_RST_CFG_MASK, 0);
> -	if (ret)
> -		return ret;
> +	if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) {

Is there a reason that there is a now a conditional check for the
compatible here?

Thanks,
Drew

Re: [PATCH v3 3/5] reset: th1520: Prepare for supporting multiple controllers

[Yao Zi]

On Wed, Oct 29, 2025 at 12:54:25PM +0000, Drew Fustini wrote:
> On Tue, Oct 14, 2025 at 01:10:30PM +0000, Yao Zi wrote:
> > TH1520 SoC is divided into several subsystems, shipping distinct reset
> > controllers with similar control logic. Let's make reset signal mapping
> > a data structure specific to one compatible to prepare for introduction
> > of more reset controllers in the future.
> > 
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> >  drivers/reset/reset-th1520.c | 42 +++++++++++++++++++++++++-----------
> >  1 file changed, 30 insertions(+), 12 deletions(-)
> > 
> > diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c
> > index 14d964a9c6b6..2b65a95ed021 100644
> > --- a/drivers/reset/reset-th1520.c
> > +++ b/drivers/reset/reset-th1520.c
> [snip]
> > @@ -138,22 +147,31 @@ static int th1520_reset_probe(struct platform_device *pdev)
> >  	if (IS_ERR(priv->map))
> >  		return PTR_ERR(priv->map);
> >  
> > -	/* Initialize GPU resets to asserted state */
> > -	ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG,
> > -				 TH1520_GPU_RST_CFG_MASK, 0);
> > -	if (ret)
> > -		return ret;
> > +	if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) {
> 
> Is there a reason that there is a now a conditional check for the
> compatible here?

Yes, this regmap operation is for initializing GPU resets and thus
modifies TH1520_GPU_RST_CFG, which only applies for the VO reset
controller (with compatible "thead,th1520-reset") but not others, or
other unrelated resets could be unexpectedly asserted.

> Thanks,
> Drew

Regards,
Yao Zi

Re: [PATCH v3 3/5] reset: th1520: Prepare for supporting multiple controllers

[Drew Fustini]

On Wed, Oct 29, 2025 at 03:13:46PM +0000, Yao Zi wrote:
> On Wed, Oct 29, 2025 at 12:54:25PM +0000, Drew Fustini wrote:
> > On Tue, Oct 14, 2025 at 01:10:30PM +0000, Yao Zi wrote:
> > > TH1520 SoC is divided into several subsystems, shipping distinct reset
> > > controllers with similar control logic. Let's make reset signal mapping
> > > a data structure specific to one compatible to prepare for introduction
> > > of more reset controllers in the future.
> > > 
> > > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > > ---
> > >  drivers/reset/reset-th1520.c | 42 +++++++++++++++++++++++++-----------
> > >  1 file changed, 30 insertions(+), 12 deletions(-)
> > > 
> > > diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c
> > > index 14d964a9c6b6..2b65a95ed021 100644
> > > --- a/drivers/reset/reset-th1520.c
> > > +++ b/drivers/reset/reset-th1520.c
> > [snip]
> > > @@ -138,22 +147,31 @@ static int th1520_reset_probe(struct platform_device *pdev)
> > >  	if (IS_ERR(priv->map))
> > >  		return PTR_ERR(priv->map);
> > >  
> > > -	/* Initialize GPU resets to asserted state */
> > > -	ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG,
> > > -				 TH1520_GPU_RST_CFG_MASK, 0);
> > > -	if (ret)
> > > -		return ret;
> > > +	if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) {
> > 
> > Is there a reason that there is a now a conditional check for the
> > compatible here?
> 
> Yes, this regmap operation is for initializing GPU resets and thus
> modifies TH1520_GPU_RST_CFG, which only applies for the VO reset
> controller (with compatible "thead,th1520-reset") but not others, or
> other unrelated resets could be unexpectedly asserted.

Thanks for the explanation.

Reviewed-by: Drew Fustini <fustini@kernel.org>

[PATCH v3 4/5] reset: th1520: Support reset controllers in more subsystems

[Yao Zi]

Introduce reset controllers for AP, MISC, VI, VP and DSP subsystems and
add their reset signal mappings.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 drivers/reset/reset-th1520.c | 793 +++++++++++++++++++++++++++++++++++
 1 file changed, 793 insertions(+)

diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c
index 2b65a95ed021..fd32e991c4cb 100644
--- a/drivers/reset/reset-th1520.c
+++ b/drivers/reset/reset-th1520.c
@@ -11,6 +11,85 @@
 
 #include <dt-bindings/reset/thead,th1520-reset.h>
 
+ /* register offset in RSTGEN_R */
+#define TH1520_BROM_RST_CFG		0x0
+#define TH1520_C910_RST_CFG		0x4
+#define TH1520_CHIP_DBG_RST_CFG		0xc
+#define TH1520_AXI4_CPUSYS2_RST_CFG	0x10
+#define TH1520_X2H_CPUSYS_RST_CFG	0x18
+#define TH1520_AHB2_CPUSYS_RST_CFG	0x1c
+#define TH1520_APB3_CPUSYS_RST_CFG	0x20
+#define TH1520_MBOX0_RST_CFG		0x24
+#define TH1520_MBOX1_RST_CFG		0x28
+#define TH1520_MBOX2_RST_CFG		0x2c
+#define TH1520_MBOX3_RST_CFG		0x30
+#define TH1520_WDT0_RST_CFG		0x34
+#define TH1520_WDT1_RST_CFG		0x38
+#define TH1520_TIMER0_RST_CFG		0x3c
+#define TH1520_TIMER1_RST_CFG		0x40
+#define TH1520_PERISYS_AHB_RST_CFG	0x44
+#define TH1520_PERISYS_APB1_RST_CFG	0x48
+#define TH1520_PERISYS_APB2_RST_CFG	0x4c
+#define TH1520_GMAC0_RST_CFG		0x68
+#define TH1520_UART0_RST_CFG		0x70
+#define TH1520_UART1_RST_CFG		0x74
+#define TH1520_UART2_RST_CFG		0x78
+#define TH1520_UART3_RST_CFG		0x7c
+#define TH1520_UART4_RST_CFG		0x80
+#define TH1520_UART5_RST_CFG		0x84
+#define TH1520_QSPI0_RST_CFG		0x8c
+#define TH1520_QSPI1_RST_CFG		0x90
+#define TH1520_SPI_RST_CFG		0x94
+#define TH1520_I2C0_RST_CFG		0x98
+#define TH1520_I2C1_RST_CFG		0x9c
+#define TH1520_I2C2_RST_CFG		0xa0
+#define TH1520_I2C3_RST_CFG		0xa4
+#define TH1520_I2C4_RST_CFG		0xa8
+#define TH1520_I2C5_RST_CFG		0xac
+#define TH1520_GPIO0_RST_CFG		0xb0
+#define TH1520_GPIO1_RST_CFG		0xb4
+#define TH1520_GPIO2_RST_CFG		0xb8
+#define TH1520_PWM_RST_CFG		0xc0
+#define TH1520_PADCTRL0_APSYS_RST_CFG	0xc4
+#define TH1520_CPU2PERI_X2H_RST_CFG	0xcc
+#define TH1520_CPU2AON_X2H_RST_CFG	0xe4
+#define TH1520_AON2CPU_A2X_RST_CFG	0xfc
+#define TH1520_NPUSYS_AXI_RST_CFG	0x128
+#define TH1520_CPU2VP_X2P_RST_CFG	0x12c
+#define TH1520_CPU2VI_X2H_RST_CFG	0x138
+#define TH1520_BMU_C910_RST_CFG		0x148
+#define TH1520_DMAC_CPUSYS_RST_CFG	0x14c
+#define TH1520_SPINLOCK_RST_CFG		0x178
+#define TH1520_CFG2TEE_X2H_RST_CFG	0x188
+#define TH1520_DSMART_RST_CFG		0x18c
+#define TH1520_GPIO3_RST_CFG		0x1a8
+#define TH1520_I2S_RST_CFG		0x1ac
+#define TH1520_IMG_NNA_RST_CFG		0x1b0
+#define TH1520_PERI_APB3_RST_CFG	0x1dc
+#define TH1520_VP_SUBSYS_RST_CFG	0x1ec
+#define TH1520_PERISYS_APB4_RST_CFG	0x1f8
+#define TH1520_GMAC1_RST_CFG		0x204
+#define TH1520_GMAC_AXI_RST_CFG		0x208
+#define TH1520_PADCTRL1_APSYS_RST_CFG	0x20c
+#define TH1520_VOSYS_AXI_RST_CFG	0x210
+#define TH1520_VOSYS_X2X_RST_CFG	0x214
+#define TH1520_MISC2VP_X2X_RST_CFG	0x218
+#define TH1520_SUBSYS_RST_CFG		0x220
+
+ /* register offset in DSP_REGMAP */
+#define TH1520_DSPSYS_RST_CFG		0x0
+
+ /* register offset in MISCSYS_REGMAP */
+#define TH1520_EMMC_RST_CFG		0x0
+#define TH1520_MISCSYS_AXI_RST_CFG	0x8
+#define TH1520_SDIO0_RST_CFG		0xc
+#define TH1520_SDIO1_RST_CFG		0x10
+#define TH1520_USB3_DRD_RST_CFG		0x14
+
+ /* register offset in VISYS_REGMAP */
+#define TH1520_VISYS_RST_CFG		0x0
+#define TH1520_VISYS_2_RST_CFG		0x4
+
  /* register offset in VOSYS_REGMAP */
 #define TH1520_GPU_RST_CFG		0x0
 #define TH1520_GPU_RST_CFG_MASK		GENMASK(1, 0)
@@ -18,6 +97,8 @@
 #define TH1520_DSI0_RST_CFG		0x8
 #define TH1520_DSI1_RST_CFG		0xc
 #define TH1520_HDMI_RST_CFG		0x14
+#define TH1520_AXI4_VO_DW_AXI_RST_CFG	0x18
+#define TH1520_X2H_X4_VOSYS_DW_RST_CFG	0x20
 
 /* register values */
 #define TH1520_GPU_SW_GPU_RST		BIT(0)
@@ -29,6 +110,13 @@
 #define TH1520_HDMI_SW_MAIN_RST		BIT(0)
 #define TH1520_HDMI_SW_PRST		BIT(1)
 
+ /* register offset in VPSYS_REGMAP */
+#define TH1520_AXIBUS_RST_CFG		0x0
+#define TH1520_FCE_RST_CFG		0x4
+#define TH1520_G2D_RST_CFG		0x8
+#define TH1520_VDEC_RST_CFG		0xc
+#define TH1520_VENC_RST_CFG		0x10
+
 struct th1520_reset_map {
 	u32 bit;
 	u32 reg;
@@ -82,6 +170,681 @@ static const struct th1520_reset_map th1520_resets[] = {
 		.bit = TH1520_HDMI_SW_PRST,
 		.reg = TH1520_HDMI_RST_CFG,
 	},
+	[TH1520_RESET_ID_VOAXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_AXI4_VO_DW_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_VOAXI_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_AXI4_VO_DW_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2H_DPU_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2H_DPU_AHB] = {
+		.bit = BIT(1),
+		.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2H_DPU1_AXI] = {
+		.bit = BIT(2),
+		.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2H_DPU1_AHB] = {
+		.bit = BIT(3),
+		.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
+	},
+};
+
+static const struct th1520_reset_map th1520_ap_resets[] = {
+	[TH1520_RESET_ID_BROM] = {
+		.bit = BIT(0),
+		.reg = TH1520_BROM_RST_CFG,
+	},
+	[TH1520_RESET_ID_C910_TOP] = {
+		.bit = BIT(0),
+		.reg = TH1520_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_NPU] =  {
+		.bit = BIT(0),
+		.reg = TH1520_IMG_NNA_RST_CFG,
+	},
+	[TH1520_RESET_ID_WDT0] = {
+		.bit = BIT(0),
+		.reg = TH1520_WDT0_RST_CFG,
+	},
+	[TH1520_RESET_ID_WDT1] = {
+		.bit = BIT(0),
+		.reg = TH1520_WDT1_RST_CFG,
+	},
+	[TH1520_RESET_ID_C910_C0] = {
+		.bit = BIT(1),
+		.reg = TH1520_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_C910_C1] = {
+		.bit = BIT(2),
+		.reg = TH1520_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_C910_C2] = {
+		.bit = BIT(3),
+		.reg = TH1520_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_C910_C3] = {
+		.bit = BIT(4),
+		.reg = TH1520_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_CHIP_DBG_CORE] = {
+		.bit = BIT(0),
+		.reg = TH1520_CHIP_DBG_RST_CFG,
+	},
+	[TH1520_RESET_ID_CHIP_DBG_AXI] = {
+		.bit = BIT(1),
+		.reg = TH1520_CHIP_DBG_RST_CFG,
+	},
+	[TH1520_RESET_ID_AXI4_CPUSYS2_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_AXI4_CPUSYS2_RST_CFG,
+	},
+	[TH1520_RESET_ID_AXI4_CPUSYS2_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_AXI4_CPUSYS2_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2H_CPUSYS] = {
+		.bit = BIT(0),
+		.reg = TH1520_X2H_CPUSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_AHB2_CPUSYS] = {
+		.bit = BIT(0),
+		.reg = TH1520_AHB2_CPUSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_APB3_CPUSYS] = {
+		.bit = BIT(0),
+		.reg = TH1520_APB3_CPUSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_MBOX0_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_MBOX0_RST_CFG,
+	},
+	[TH1520_RESET_ID_MBOX1_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_MBOX1_RST_CFG,
+	},
+	[TH1520_RESET_ID_MBOX2_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_MBOX2_RST_CFG,
+	},
+	[TH1520_RESET_ID_MBOX3_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_MBOX3_RST_CFG,
+	},
+	[TH1520_RESET_ID_TIMER0_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_TIMER0_RST_CFG,
+	},
+	[TH1520_RESET_ID_TIMER0_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_TIMER0_RST_CFG,
+	},
+	[TH1520_RESET_ID_TIMER1_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_TIMER1_RST_CFG,
+	},
+	[TH1520_RESET_ID_TIMER1_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_TIMER1_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERISYS_AHB] = {
+		.bit = BIT(0),
+		.reg = TH1520_PERISYS_AHB_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERISYS_APB1] = {
+		.bit = BIT(0),
+		.reg = TH1520_PERISYS_APB1_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERISYS_APB2] = {
+		.bit = BIT(0),
+		.reg = TH1520_PERISYS_APB2_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC0_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_GMAC0_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC0_AHB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GMAC0_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC0_CLKGEN] = {
+		.bit = BIT(2),
+		.reg = TH1520_GMAC0_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC0_AXI] = {
+		.bit = BIT(3),
+		.reg = TH1520_GMAC0_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART0_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_UART0_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART0_IF] = {
+		.bit = BIT(1),
+		.reg = TH1520_UART0_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART1_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_UART1_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART1_IF] = {
+		.bit = BIT(1),
+		.reg = TH1520_UART1_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART2_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_UART2_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART2_IF] = {
+		.bit = BIT(1),
+		.reg = TH1520_UART2_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART3_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_UART3_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART3_IF] = {
+		.bit = BIT(1),
+		.reg = TH1520_UART3_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART4_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_UART4_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART4_IF] = {
+		.bit = BIT(1),
+		.reg = TH1520_UART4_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART5_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_UART5_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART5_IF] = {
+		.bit = BIT(1),
+		.reg = TH1520_UART5_RST_CFG,
+	},
+	[TH1520_RESET_ID_QSPI0_IF] = {
+		.bit = BIT(0),
+		.reg = TH1520_QSPI0_RST_CFG,
+	},
+	[TH1520_RESET_ID_QSPI0_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_QSPI0_RST_CFG,
+	},
+	[TH1520_RESET_ID_QSPI1_IF] = {
+		.bit = BIT(0),
+		.reg = TH1520_QSPI1_RST_CFG,
+	},
+	[TH1520_RESET_ID_QSPI1_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_QSPI1_RST_CFG,
+	},
+	[TH1520_RESET_ID_SPI_IF] = {
+		.bit = BIT(0),
+		.reg = TH1520_SPI_RST_CFG,
+	},
+	[TH1520_RESET_ID_SPI_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_SPI_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C0_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2C0_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C0_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_I2C0_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C1_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2C1_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C1_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_I2C1_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C2_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2C2_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C2_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_I2C2_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C3_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2C3_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C3_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_I2C3_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C4_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2C4_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C4_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_I2C4_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C5_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2C5_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C5_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_I2C5_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO0_DB] = {
+		.bit = BIT(0),
+		.reg = TH1520_GPIO0_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO0_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GPIO0_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO1_DB] = {
+		.bit = BIT(0),
+		.reg = TH1520_GPIO1_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO1_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GPIO1_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO2_DB] = {
+		.bit = BIT(0),
+		.reg = TH1520_GPIO2_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO2_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GPIO2_RST_CFG,
+	},
+	[TH1520_RESET_ID_PWM_COUNTER] = {
+		.bit = BIT(0),
+		.reg = TH1520_PWM_RST_CFG,
+	},
+	[TH1520_RESET_ID_PWM_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_PWM_RST_CFG,
+	},
+	[TH1520_RESET_ID_PADCTRL0_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_PADCTRL0_APSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_CPU2PERI_X2H] = {
+		.bit = BIT(1),
+		.reg = TH1520_CPU2PERI_X2H_RST_CFG,
+	},
+	[TH1520_RESET_ID_CPU2AON_X2H] = {
+		.bit = BIT(0),
+		.reg = TH1520_CPU2AON_X2H_RST_CFG,
+	},
+	[TH1520_RESET_ID_AON2CPU_A2X] = {
+		.bit = BIT(0),
+		.reg = TH1520_AON2CPU_A2X_RST_CFG,
+	},
+	[TH1520_RESET_ID_NPUSYS_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_NPUSYS_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_NPUSYS_AXI_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_NPUSYS_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_CPU2VP_X2P] = {
+		.bit = BIT(0),
+		.reg = TH1520_CPU2VP_X2P_RST_CFG,
+	},
+	[TH1520_RESET_ID_CPU2VI_X2H] = {
+		.bit = BIT(0),
+		.reg = TH1520_CPU2VI_X2H_RST_CFG,
+	},
+	[TH1520_RESET_ID_BMU_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_BMU_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_BMU_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_BMU_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_DMAC_CPUSYS_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_DMAC_CPUSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DMAC_CPUSYS_AHB] = {
+		.bit = BIT(1),
+		.reg = TH1520_DMAC_CPUSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_SPINLOCK] = {
+		.bit = BIT(0),
+		.reg = TH1520_SPINLOCK_RST_CFG,
+	},
+	[TH1520_RESET_ID_CFG2TEE] = {
+		.bit = BIT(0),
+		.reg = TH1520_CFG2TEE_X2H_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSMART] = {
+		.bit = BIT(0),
+		.reg = TH1520_DSMART_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO3_DB] = {
+		.bit = BIT(0),
+		.reg = TH1520_GPIO3_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO3_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GPIO3_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERI_I2S] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2S_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERI_APB3] = {
+		.bit = BIT(0),
+		.reg = TH1520_PERI_APB3_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERI2PERI1_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_PERI_APB3_RST_CFG,
+	},
+	[TH1520_RESET_ID_VPSYS_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_VP_SUBSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERISYS_APB4] = {
+		.bit = BIT(0),
+		.reg = TH1520_PERISYS_APB4_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC1_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_GMAC1_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC1_AHB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GMAC1_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC1_CLKGEN] = {
+		.bit = BIT(2),
+		.reg = TH1520_GMAC1_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC1_AXI] = {
+		.bit = BIT(3),
+		.reg = TH1520_GMAC1_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_GMAC_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC_AXI_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GMAC_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_PADCTRL1_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_PADCTRL1_APSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VOSYS_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_VOSYS_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_VOSYS_AXI_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_VOSYS_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_VOSYS_AXI_X2X] = {
+		.bit = BIT(0),
+		.reg = TH1520_VOSYS_X2X_RST_CFG,
+	},
+	[TH1520_RESET_ID_MISC2VP_X2X] = {
+		.bit = BIT(0),
+		.reg = TH1520_MISC2VP_X2X_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSPSYS] = {
+		.bit = BIT(0),
+		.reg = TH1520_SUBSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VISYS] = {
+		.bit = BIT(1),
+		.reg = TH1520_SUBSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VOSYS] = {
+		.bit = BIT(2),
+		.reg = TH1520_SUBSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VPSYS] = {
+		.bit = BIT(3),
+		.reg = TH1520_SUBSYS_RST_CFG,
+	},
+};
+
+static const struct th1520_reset_map th1520_dsp_resets[] = {
+	[TH1520_RESET_ID_X2X_DSP1] = {
+		.bit = BIT(0),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2X_DSP0] = {
+		.bit = BIT(1),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2X_SLAVE_DSP1] = {
+		.bit = BIT(2),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2X_SLAVE_DSP0] = {
+		.bit = BIT(3),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSP0_CORE] = {
+		.bit = BIT(8),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSP0_DEBUG] = {
+		.bit = BIT(9),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSP0_APB] = {
+		.bit = BIT(10),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSP1_CORE] = {
+		.bit = BIT(12),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSP1_DEBUG] = {
+		.bit = BIT(13),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSP1_APB] = {
+		.bit = BIT(14),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSPSYS_APB] = {
+		.bit = BIT(16),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_AXI4_DSPSYS_SLV] = {
+		.bit = BIT(20),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_AXI4_DSPSYS] = {
+		.bit = BIT(24),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_AXI4_DSP_RS] = {
+		.bit = BIT(26),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+};
+
+static const struct th1520_reset_map th1520_misc_resets[] = {
+	[TH1520_RESET_ID_EMMC_SDIO_CLKGEN] = {
+		.bit = BIT(0),
+		.reg = TH1520_EMMC_RST_CFG,
+	},
+	[TH1520_RESET_ID_EMMC] = {
+		.bit = BIT(1),
+		.reg = TH1520_EMMC_RST_CFG,
+	},
+	[TH1520_RESET_ID_MISCSYS_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_MISCSYS_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_MISCSYS_AXI_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_MISCSYS_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_SDIO0] = {
+		.bit = BIT(0),
+		.reg = TH1520_SDIO0_RST_CFG,
+	},
+	[TH1520_RESET_ID_SDIO1] = {
+		.bit = BIT(1),
+		.reg = TH1520_SDIO1_RST_CFG,
+	},
+	[TH1520_RESET_ID_USB3_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_USB3_DRD_RST_CFG,
+	},
+	[TH1520_RESET_ID_USB3_PHY] = {
+		.bit = BIT(1),
+		.reg = TH1520_USB3_DRD_RST_CFG,
+	},
+	[TH1520_RESET_ID_USB3_VCC] = {
+		.bit = BIT(2),
+		.reg = TH1520_USB3_DRD_RST_CFG,
+	},
+};
+
+static const struct th1520_reset_map th1520_vi_resets[] = {
+	[TH1520_RESET_ID_ISP0] = {
+		.bit = BIT(0),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_ISP1] = {
+		.bit = BIT(4),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_CSI0_APB] = {
+		.bit = BIT(16),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_CSI1_APB] = {
+		.bit = BIT(17),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_CSI2_APB] = {
+		.bit = BIT(18),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_MIPI_FIFO] = {
+		.bit = BIT(20),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_ISP_VENC_APB] = {
+		.bit = BIT(24),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VIPRE_APB] = {
+		.bit = BIT(28),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VIPRE_AXI] = {
+		.bit = BIT(29),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DW200_APB] = {
+		.bit = BIT(31),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VISYS3_AXI] = {
+		.bit = BIT(8),
+		.reg = TH1520_VISYS_2_RST_CFG,
+	},
+	[TH1520_RESET_ID_VISYS2_AXI] = {
+		.bit = BIT(9),
+		.reg = TH1520_VISYS_2_RST_CFG,
+	},
+	[TH1520_RESET_ID_VISYS1_AXI] = {
+		.bit = BIT(10),
+		.reg = TH1520_VISYS_2_RST_CFG,
+	},
+	[TH1520_RESET_ID_VISYS_AXI] = {
+		.bit = BIT(12),
+		.reg = TH1520_VISYS_2_RST_CFG,
+	},
+	[TH1520_RESET_ID_VISYS_APB] = {
+		.bit = BIT(16),
+		.reg = TH1520_VISYS_2_RST_CFG,
+	},
+	[TH1520_RESET_ID_ISP_VENC_AXI] = {
+		.bit = BIT(20),
+		.reg = TH1520_VISYS_2_RST_CFG,
+	},
+};
+
+static const struct th1520_reset_map th1520_vp_resets[] = {
+	[TH1520_RESET_ID_VPSYS_AXI_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_AXIBUS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VPSYS_AXI] = {
+		.bit = BIT(1),
+		.reg = TH1520_AXIBUS_RST_CFG,
+	},
+	[TH1520_RESET_ID_FCE_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_FCE_RST_CFG,
+	},
+	[TH1520_RESET_ID_FCE_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_FCE_RST_CFG,
+	},
+	[TH1520_RESET_ID_FCE_X2X_MASTER] = {
+		.bit = BIT(4),
+		.reg = TH1520_FCE_RST_CFG,
+	},
+	[TH1520_RESET_ID_FCE_X2X_SLAVE] = {
+		.bit = BIT(5),
+		.reg = TH1520_FCE_RST_CFG,
+	},
+	[TH1520_RESET_ID_G2D_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_G2D_RST_CFG,
+	},
+	[TH1520_RESET_ID_G2D_ACLK] = {
+		.bit = BIT(1),
+		.reg = TH1520_G2D_RST_CFG,
+	},
+	[TH1520_RESET_ID_G2D_CORE] = {
+		.bit = BIT(2),
+		.reg = TH1520_G2D_RST_CFG,
+	},
+	[TH1520_RESET_ID_VDEC_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_VDEC_RST_CFG,
+	},
+	[TH1520_RESET_ID_VDEC_ACLK] = {
+		.bit = BIT(1),
+		.reg = TH1520_VDEC_RST_CFG,
+	},
+	[TH1520_RESET_ID_VDEC_CORE] = {
+		.bit = BIT(2),
+		.reg = TH1520_VDEC_RST_CFG,
+	},
+	[TH1520_RESET_ID_VENC_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_VENC_RST_CFG,
+	},
+	[TH1520_RESET_ID_VENC_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_VENC_RST_CFG,
+	},
 };
 
 static inline struct th1520_reset_priv *
@@ -170,8 +933,38 @@ static const struct th1520_reset_data th1520_reset_data = {
 	.num = ARRAY_SIZE(th1520_resets),
 };
 
+static const struct th1520_reset_data th1520_ap_reset_data = {
+	.resets = th1520_ap_resets,
+	.num = ARRAY_SIZE(th1520_ap_resets),
+};
+
+static const struct th1520_reset_data th1520_dsp_reset_data = {
+	.resets = th1520_dsp_resets,
+	.num = ARRAY_SIZE(th1520_dsp_resets),
+};
+
+static const struct th1520_reset_data th1520_misc_reset_data = {
+	.resets = th1520_misc_resets,
+	.num = ARRAY_SIZE(th1520_misc_resets),
+};
+
+static const struct th1520_reset_data th1520_vi_reset_data = {
+	.resets = th1520_vi_resets,
+	.num = ARRAY_SIZE(th1520_vi_resets),
+};
+
+static const struct th1520_reset_data th1520_vp_reset_data = {
+	.resets = th1520_vp_resets,
+	.num = ARRAY_SIZE(th1520_vp_resets),
+};
+
 static const struct of_device_id th1520_reset_match[] = {
 	{ .compatible = "thead,th1520-reset", .data = &th1520_reset_data },
+	{ .compatible = "thead,th1520-reset-ap", .data = &th1520_ap_reset_data },
+	{ .compatible = "thead,th1520-reset-dsp", .data = &th1520_dsp_reset_data },
+	{ .compatible = "thead,th1520-reset-misc", .data = &th1520_misc_reset_data },
+	{ .compatible = "thead,th1520-reset-vi", .data = &th1520_vi_reset_data },
+	{ .compatible = "thead,th1520-reset-vp", .data = &th1520_vp_reset_data },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, th1520_reset_match);
-- 
2.50.1

Re: [PATCH v3 4/5] reset: th1520: Support reset controllers in more subsystems

[Guo Ren]

On Tue, Oct 14, 2025 at 9:12 PM Yao Zi <ziyao@disroot.org> wrote:
>
> Introduce reset controllers for AP, MISC, VI, VP and DSP subsystems and
> add their reset signal mappings.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  drivers/reset/reset-th1520.c | 793 +++++++++++++++++++++++++++++++++++
>  1 file changed, 793 insertions(+)
>
> diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c
> index 2b65a95ed021..fd32e991c4cb 100644
> --- a/drivers/reset/reset-th1520.c
> +++ b/drivers/reset/reset-th1520.c
> @@ -11,6 +11,85 @@
>
>  #include <dt-bindings/reset/thead,th1520-reset.h>
>
> + /* register offset in RSTGEN_R */
> +#define TH1520_BROM_RST_CFG            0x0
> +#define TH1520_C910_RST_CFG            0x4
> +#define TH1520_CHIP_DBG_RST_CFG                0xc
> +#define TH1520_AXI4_CPUSYS2_RST_CFG    0x10
> +#define TH1520_X2H_CPUSYS_RST_CFG      0x18
> +#define TH1520_AHB2_CPUSYS_RST_CFG     0x1c
> +#define TH1520_APB3_CPUSYS_RST_CFG     0x20
> +#define TH1520_MBOX0_RST_CFG           0x24
> +#define TH1520_MBOX1_RST_CFG           0x28
> +#define TH1520_MBOX2_RST_CFG           0x2c
> +#define TH1520_MBOX3_RST_CFG           0x30
> +#define TH1520_WDT0_RST_CFG            0x34
> +#define TH1520_WDT1_RST_CFG            0x38
> +#define TH1520_TIMER0_RST_CFG          0x3c
> +#define TH1520_TIMER1_RST_CFG          0x40
> +#define TH1520_PERISYS_AHB_RST_CFG     0x44
> +#define TH1520_PERISYS_APB1_RST_CFG    0x48
> +#define TH1520_PERISYS_APB2_RST_CFG    0x4c
> +#define TH1520_GMAC0_RST_CFG           0x68
> +#define TH1520_UART0_RST_CFG           0x70
> +#define TH1520_UART1_RST_CFG           0x74
> +#define TH1520_UART2_RST_CFG           0x78
> +#define TH1520_UART3_RST_CFG           0x7c
> +#define TH1520_UART4_RST_CFG           0x80
> +#define TH1520_UART5_RST_CFG           0x84
> +#define TH1520_QSPI0_RST_CFG           0x8c
> +#define TH1520_QSPI1_RST_CFG           0x90
> +#define TH1520_SPI_RST_CFG             0x94
> +#define TH1520_I2C0_RST_CFG            0x98
> +#define TH1520_I2C1_RST_CFG            0x9c
> +#define TH1520_I2C2_RST_CFG            0xa0
> +#define TH1520_I2C3_RST_CFG            0xa4
> +#define TH1520_I2C4_RST_CFG            0xa8
> +#define TH1520_I2C5_RST_CFG            0xac
> +#define TH1520_GPIO0_RST_CFG           0xb0
> +#define TH1520_GPIO1_RST_CFG           0xb4
> +#define TH1520_GPIO2_RST_CFG           0xb8
> +#define TH1520_PWM_RST_CFG             0xc0
> +#define TH1520_PADCTRL0_APSYS_RST_CFG  0xc4
> +#define TH1520_CPU2PERI_X2H_RST_CFG    0xcc
> +#define TH1520_CPU2AON_X2H_RST_CFG     0xe4
> +#define TH1520_AON2CPU_A2X_RST_CFG     0xfc
> +#define TH1520_NPUSYS_AXI_RST_CFG      0x128
> +#define TH1520_CPU2VP_X2P_RST_CFG      0x12c
> +#define TH1520_CPU2VI_X2H_RST_CFG      0x138
> +#define TH1520_BMU_C910_RST_CFG                0x148
> +#define TH1520_DMAC_CPUSYS_RST_CFG     0x14c
> +#define TH1520_SPINLOCK_RST_CFG                0x178
> +#define TH1520_CFG2TEE_X2H_RST_CFG     0x188
> +#define TH1520_DSMART_RST_CFG          0x18c
> +#define TH1520_GPIO3_RST_CFG           0x1a8
> +#define TH1520_I2S_RST_CFG             0x1ac
> +#define TH1520_IMG_NNA_RST_CFG         0x1b0
> +#define TH1520_PERI_APB3_RST_CFG       0x1dc
> +#define TH1520_VP_SUBSYS_RST_CFG       0x1ec
> +#define TH1520_PERISYS_APB4_RST_CFG    0x1f8
> +#define TH1520_GMAC1_RST_CFG           0x204
> +#define TH1520_GMAC_AXI_RST_CFG                0x208
> +#define TH1520_PADCTRL1_APSYS_RST_CFG  0x20c
> +#define TH1520_VOSYS_AXI_RST_CFG       0x210
> +#define TH1520_VOSYS_X2X_RST_CFG       0x214
> +#define TH1520_MISC2VP_X2X_RST_CFG     0x218
> +#define TH1520_SUBSYS_RST_CFG          0x220
> +
> + /* register offset in DSP_REGMAP */
> +#define TH1520_DSPSYS_RST_CFG          0x0
> +
> + /* register offset in MISCSYS_REGMAP */
> +#define TH1520_EMMC_RST_CFG            0x0
> +#define TH1520_MISCSYS_AXI_RST_CFG     0x8
> +#define TH1520_SDIO0_RST_CFG           0xc
> +#define TH1520_SDIO1_RST_CFG           0x10
> +#define TH1520_USB3_DRD_RST_CFG                0x14
> +
> + /* register offset in VISYS_REGMAP */
> +#define TH1520_VISYS_RST_CFG           0x0
> +#define TH1520_VISYS_2_RST_CFG         0x4
> +
>   /* register offset in VOSYS_REGMAP */
>  #define TH1520_GPU_RST_CFG             0x0
>  #define TH1520_GPU_RST_CFG_MASK                GENMASK(1, 0)
> @@ -18,6 +97,8 @@
>  #define TH1520_DSI0_RST_CFG            0x8
>  #define TH1520_DSI1_RST_CFG            0xc
>  #define TH1520_HDMI_RST_CFG            0x14
> +#define TH1520_AXI4_VO_DW_AXI_RST_CFG  0x18
> +#define TH1520_X2H_X4_VOSYS_DW_RST_CFG 0x20
>
>  /* register values */
>  #define TH1520_GPU_SW_GPU_RST          BIT(0)
> @@ -29,6 +110,13 @@
>  #define TH1520_HDMI_SW_MAIN_RST                BIT(0)
>  #define TH1520_HDMI_SW_PRST            BIT(1)
>
> + /* register offset in VPSYS_REGMAP */
> +#define TH1520_AXIBUS_RST_CFG          0x0
> +#define TH1520_FCE_RST_CFG             0x4
> +#define TH1520_G2D_RST_CFG             0x8
> +#define TH1520_VDEC_RST_CFG            0xc
> +#define TH1520_VENC_RST_CFG            0x10
> +
>  struct th1520_reset_map {
>         u32 bit;
>         u32 reg;
> @@ -82,6 +170,681 @@ static const struct th1520_reset_map th1520_resets[] = {
>                 .bit = TH1520_HDMI_SW_PRST,
>                 .reg = TH1520_HDMI_RST_CFG,
>         },
> +       [TH1520_RESET_ID_VOAXI] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VOAXI_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_X2H_DPU_AXI] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_X2H_DPU_AHB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_X2H_DPU1_AXI] = {
> +               .bit = BIT(2),
> +               .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_X2H_DPU1_AHB] = {
> +               .bit = BIT(3),
> +               .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
> +       },
> +};
> +
> +static const struct th1520_reset_map th1520_ap_resets[] = {
> +       [TH1520_RESET_ID_BROM] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_BROM_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_C910_TOP] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_C910_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_NPU] =  {
> +               .bit = BIT(0),
> +               .reg = TH1520_IMG_NNA_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_WDT0] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_WDT0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_WDT1] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_WDT1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_C910_C0] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_C910_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_C910_C1] = {
> +               .bit = BIT(2),
> +               .reg = TH1520_C910_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_C910_C2] = {
> +               .bit = BIT(3),
> +               .reg = TH1520_C910_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_C910_C3] = {
> +               .bit = BIT(4),
> +               .reg = TH1520_C910_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_CHIP_DBG_CORE] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_CHIP_DBG_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_CHIP_DBG_AXI] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_CHIP_DBG_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_AXI4_CPUSYS2_AXI] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_AXI4_CPUSYS2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_AXI4_CPUSYS2_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_AXI4_CPUSYS2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_X2H_CPUSYS] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_X2H_CPUSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_AHB2_CPUSYS] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_AHB2_CPUSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_APB3_CPUSYS] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_APB3_CPUSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_MBOX0_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_MBOX0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_MBOX1_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_MBOX1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_MBOX2_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_MBOX2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_MBOX3_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_MBOX3_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_TIMER0_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_TIMER0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_TIMER0_CORE] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_TIMER0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_TIMER1_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_TIMER1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_TIMER1_CORE] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_TIMER1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_PERISYS_AHB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_PERISYS_AHB_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_PERISYS_APB1] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_PERISYS_APB1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_PERISYS_APB2] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_PERISYS_APB2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GMAC0_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_GMAC0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GMAC0_AHB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_GMAC0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GMAC0_CLKGEN] = {
> +               .bit = BIT(2),
> +               .reg = TH1520_GMAC0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GMAC0_AXI] = {
> +               .bit = BIT(3),
> +               .reg = TH1520_GMAC0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_UART0_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_UART0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_UART0_IF] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_UART0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_UART1_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_UART1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_UART1_IF] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_UART1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_UART2_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_UART2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_UART2_IF] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_UART2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_UART3_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_UART3_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_UART3_IF] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_UART3_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_UART4_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_UART4_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_UART4_IF] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_UART4_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_UART5_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_UART5_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_UART5_IF] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_UART5_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_QSPI0_IF] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_QSPI0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_QSPI0_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_QSPI0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_QSPI1_IF] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_QSPI1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_QSPI1_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_QSPI1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_SPI_IF] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_SPI_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_SPI_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_SPI_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_I2C0_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_I2C0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_I2C0_CORE] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_I2C0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_I2C1_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_I2C1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_I2C1_CORE] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_I2C1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_I2C2_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_I2C2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_I2C2_CORE] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_I2C2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_I2C3_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_I2C3_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_I2C3_CORE] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_I2C3_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_I2C4_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_I2C4_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_I2C4_CORE] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_I2C4_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_I2C5_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_I2C5_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_I2C5_CORE] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_I2C5_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GPIO0_DB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_GPIO0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GPIO0_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_GPIO0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GPIO1_DB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_GPIO1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GPIO1_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_GPIO1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GPIO2_DB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_GPIO2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GPIO2_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_GPIO2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_PWM_COUNTER] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_PWM_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_PWM_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_PWM_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_PADCTRL0_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_PADCTRL0_APSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_CPU2PERI_X2H] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_CPU2PERI_X2H_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_CPU2AON_X2H] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_CPU2AON_X2H_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_AON2CPU_A2X] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_AON2CPU_A2X_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_NPUSYS_AXI] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_NPUSYS_AXI_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_NPUSYS_AXI_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_NPUSYS_AXI_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_CPU2VP_X2P] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_CPU2VP_X2P_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_CPU2VI_X2H] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_CPU2VI_X2H_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_BMU_AXI] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_BMU_C910_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_BMU_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_BMU_C910_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_DMAC_CPUSYS_AXI] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_DMAC_CPUSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_DMAC_CPUSYS_AHB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_DMAC_CPUSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_SPINLOCK] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_SPINLOCK_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_CFG2TEE] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_CFG2TEE_X2H_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_DSMART] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_DSMART_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GPIO3_DB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_GPIO3_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GPIO3_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_GPIO3_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_PERI_I2S] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_I2S_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_PERI_APB3] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_PERI_APB3_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_PERI2PERI1_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_PERI_APB3_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VPSYS_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_VP_SUBSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_PERISYS_APB4] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_PERISYS_APB4_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GMAC1_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_GMAC1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GMAC1_AHB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_GMAC1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GMAC1_CLKGEN] = {
> +               .bit = BIT(2),
> +               .reg = TH1520_GMAC1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GMAC1_AXI] = {
> +               .bit = BIT(3),
> +               .reg = TH1520_GMAC1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GMAC_AXI] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_GMAC_AXI_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_GMAC_AXI_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_GMAC_AXI_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_PADCTRL1_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_PADCTRL1_APSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VOSYS_AXI] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_VOSYS_AXI_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VOSYS_AXI_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_VOSYS_AXI_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VOSYS_AXI_X2X] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_VOSYS_X2X_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_MISC2VP_X2X] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_MISC2VP_X2X_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_DSPSYS] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_SUBSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VISYS] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_SUBSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VOSYS] = {
> +               .bit = BIT(2),
> +               .reg = TH1520_SUBSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VPSYS] = {
> +               .bit = BIT(3),
> +               .reg = TH1520_SUBSYS_RST_CFG,
> +       },
> +};
> +
> +static const struct th1520_reset_map th1520_dsp_resets[] = {
> +       [TH1520_RESET_ID_X2X_DSP1] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_X2X_DSP0] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_X2X_SLAVE_DSP1] = {
> +               .bit = BIT(2),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_X2X_SLAVE_DSP0] = {
> +               .bit = BIT(3),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_DSP0_CORE] = {
> +               .bit = BIT(8),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_DSP0_DEBUG] = {
> +               .bit = BIT(9),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_DSP0_APB] = {
> +               .bit = BIT(10),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_DSP1_CORE] = {
> +               .bit = BIT(12),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_DSP1_DEBUG] = {
> +               .bit = BIT(13),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_DSP1_APB] = {
> +               .bit = BIT(14),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_DSPSYS_APB] = {
> +               .bit = BIT(16),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_AXI4_DSPSYS_SLV] = {
> +               .bit = BIT(20),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_AXI4_DSPSYS] = {
> +               .bit = BIT(24),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_AXI4_DSP_RS] = {
> +               .bit = BIT(26),
> +               .reg = TH1520_DSPSYS_RST_CFG,
> +       },
> +};
> +
> +static const struct th1520_reset_map th1520_misc_resets[] = {
> +       [TH1520_RESET_ID_EMMC_SDIO_CLKGEN] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_EMMC_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_EMMC] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_EMMC_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_MISCSYS_AXI] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_MISCSYS_AXI_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_MISCSYS_AXI_APB] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_MISCSYS_AXI_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_SDIO0] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_SDIO0_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_SDIO1] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_SDIO1_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_USB3_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_USB3_DRD_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_USB3_PHY] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_USB3_DRD_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_USB3_VCC] = {
> +               .bit = BIT(2),
> +               .reg = TH1520_USB3_DRD_RST_CFG,
> +       },
> +};
> +
> +static const struct th1520_reset_map th1520_vi_resets[] = {
> +       [TH1520_RESET_ID_ISP0] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_VISYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_ISP1] = {
> +               .bit = BIT(4),
> +               .reg = TH1520_VISYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_CSI0_APB] = {
> +               .bit = BIT(16),
> +               .reg = TH1520_VISYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_CSI1_APB] = {
> +               .bit = BIT(17),
> +               .reg = TH1520_VISYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_CSI2_APB] = {
> +               .bit = BIT(18),
> +               .reg = TH1520_VISYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_MIPI_FIFO] = {
> +               .bit = BIT(20),
> +               .reg = TH1520_VISYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_ISP_VENC_APB] = {
> +               .bit = BIT(24),
> +               .reg = TH1520_VISYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VIPRE_APB] = {
> +               .bit = BIT(28),
> +               .reg = TH1520_VISYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VIPRE_AXI] = {
> +               .bit = BIT(29),
> +               .reg = TH1520_VISYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_DW200_APB] = {
> +               .bit = BIT(31),
> +               .reg = TH1520_VISYS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VISYS3_AXI] = {
> +               .bit = BIT(8),
> +               .reg = TH1520_VISYS_2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VISYS2_AXI] = {
> +               .bit = BIT(9),
> +               .reg = TH1520_VISYS_2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VISYS1_AXI] = {
> +               .bit = BIT(10),
> +               .reg = TH1520_VISYS_2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VISYS_AXI] = {
> +               .bit = BIT(12),
> +               .reg = TH1520_VISYS_2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VISYS_APB] = {
> +               .bit = BIT(16),
> +               .reg = TH1520_VISYS_2_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_ISP_VENC_AXI] = {
> +               .bit = BIT(20),
> +               .reg = TH1520_VISYS_2_RST_CFG,
> +       },
> +};
> +
> +static const struct th1520_reset_map th1520_vp_resets[] = {
> +       [TH1520_RESET_ID_VPSYS_AXI_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_AXIBUS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VPSYS_AXI] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_AXIBUS_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_FCE_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_FCE_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_FCE_CORE] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_FCE_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_FCE_X2X_MASTER] = {
> +               .bit = BIT(4),
> +               .reg = TH1520_FCE_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_FCE_X2X_SLAVE] = {
> +               .bit = BIT(5),
> +               .reg = TH1520_FCE_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_G2D_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_G2D_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_G2D_ACLK] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_G2D_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_G2D_CORE] = {
> +               .bit = BIT(2),
> +               .reg = TH1520_G2D_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VDEC_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_VDEC_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VDEC_ACLK] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_VDEC_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VDEC_CORE] = {
> +               .bit = BIT(2),
> +               .reg = TH1520_VDEC_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VENC_APB] = {
> +               .bit = BIT(0),
> +               .reg = TH1520_VENC_RST_CFG,
> +       },
> +       [TH1520_RESET_ID_VENC_CORE] = {
> +               .bit = BIT(1),
> +               .reg = TH1520_VENC_RST_CFG,
> +       },
>  };
>
>  static inline struct th1520_reset_priv *
> @@ -170,8 +933,38 @@ static const struct th1520_reset_data th1520_reset_data = {
>         .num = ARRAY_SIZE(th1520_resets),
>  };
>
> +static const struct th1520_reset_data th1520_ap_reset_data = {
> +       .resets = th1520_ap_resets,
> +       .num = ARRAY_SIZE(th1520_ap_resets),
> +};
> +
> +static const struct th1520_reset_data th1520_dsp_reset_data = {
> +       .resets = th1520_dsp_resets,
> +       .num = ARRAY_SIZE(th1520_dsp_resets),
> +};
> +
> +static const struct th1520_reset_data th1520_misc_reset_data = {
> +       .resets = th1520_misc_resets,
> +       .num = ARRAY_SIZE(th1520_misc_resets),
> +};
> +
> +static const struct th1520_reset_data th1520_vi_reset_data = {
> +       .resets = th1520_vi_resets,
> +       .num = ARRAY_SIZE(th1520_vi_resets),
> +};
> +
> +static const struct th1520_reset_data th1520_vp_reset_data = {
> +       .resets = th1520_vp_resets,
> +       .num = ARRAY_SIZE(th1520_vp_resets),
> +};
> +
>  static const struct of_device_id th1520_reset_match[] = {
>         { .compatible = "thead,th1520-reset", .data = &th1520_reset_data },
> +       { .compatible = "thead,th1520-reset-ap", .data = &th1520_ap_reset_data },
> +       { .compatible = "thead,th1520-reset-dsp", .data = &th1520_dsp_reset_data },
> +       { .compatible = "thead,th1520-reset-misc", .data = &th1520_misc_reset_data },
> +       { .compatible = "thead,th1520-reset-vi", .data = &th1520_vi_reset_data },
> +       { .compatible = "thead,th1520-reset-vp", .data = &th1520_vp_reset_data },
>         { /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, th1520_reset_match);
> --
> 2.50.1
>
LGTM!

Acked-by: Guo Ren <guoren@kernel.org>

-- 
Best Regards
 Guo Ren

Re: [PATCH v3 4/5] reset: th1520: Support reset controllers in more subsystems

[Drew Fustini]

On Tue, Oct 14, 2025 at 01:10:31PM +0000, Yao Zi wrote:
> Introduce reset controllers for AP, MISC, VI, VP and DSP subsystems and
> add their reset signal mappings.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  drivers/reset/reset-th1520.c | 793 +++++++++++++++++++++++++++++++++++
>  1 file changed, 793 insertions(+)

Reviewed-by: Drew Fustini <fustini@kernel.org>

[PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520

[Yao Zi]

Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
one for AO subsystem is marked as reserved, since it may be used by AON
firmware.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index e680d1a7c821..15d64eaea89f 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -277,6 +277,12 @@ clint: timer@ffdc000000 {
 					      <&cpu3_intc 3>, <&cpu3_intc 7>;
 		};
 
+		rst_vi: reset-controller@ffe4040100 {
+			compatible = "thead,th1520-reset-vi";
+			reg = <0xff 0xe4040100 0x0 0x8>;
+			#reset-cells = <1>;
+		};
+
 		spi0: spi@ffe700c000 {
 			compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
 			reg = <0xff 0xe700c000 0x0 0x1000>;
@@ -502,6 +508,18 @@ uart2: serial@ffec010000 {
 			status = "disabled";
 		};
 
+		rst_misc: reset-controller@ffec02c000 {
+			compatible = "thead,th1520-reset-misc";
+			reg = <0xff 0xec02c000 0x0 0x18>;
+			#reset-cells = <1>;
+		};
+
+		rst_vp: reset-controller@ffecc30000 {
+			compatible = "thead,th1520-reset-vp";
+			reg = <0xff 0xecc30000 0x0 0x14>;
+			#reset-cells = <1>;
+		};
+
 		clk: clock-controller@ffef010000 {
 			compatible = "thead,th1520-clk-ap";
 			reg = <0xff 0xef010000 0x0 0x1000>;
@@ -509,6 +527,18 @@ clk: clock-controller@ffef010000 {
 			#clock-cells = <1>;
 		};
 
+		rst_ap: reset-controller@ffef014000 {
+			compatible = "thead,th1520-reset-ap";
+			reg = <0xff 0xef014000 0x0 0x1000>;
+			#reset-cells = <1>;
+		};
+
+		rst_dsp: reset-controller@ffef040028 {
+			compatible = "thead,th1520-reset-dsp";
+			reg = <0xff 0xef040028 0x0 0x4>;
+			#reset-cells = <1>;
+		};
+
 		gpu: gpu@ffef400000 {
 			compatible = "thead,th1520-gpu", "img,img-bxm-4-64",
 				     "img,img-rogue";
@@ -681,6 +711,13 @@ aogpio: gpio-controller@0 {
 			};
 		};
 
+		rst_ao: reset-controller@fffff44000 {
+			compatible = "thead,th1520-reset-ao";
+			reg = <0xff 0xfff44000 0x0 0x2000>;
+			#reset-cells = <1>;
+			status = "reserved";
+		};
+
 		padctrl_aosys: pinctrl@fffff4a000 {
 			compatible = "thead,th1520-pinctrl";
 			reg = <0xff 0xfff4a000 0x0 0x2000>;
-- 
2.50.1

Re: [PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520

[Guo Ren]

On Tue, Oct 14, 2025 at 9:12 PM Yao Zi <ziyao@disroot.org> wrote:
>
> Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
> one for AO subsystem is marked as reserved, since it may be used by AON
> firmware.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index e680d1a7c821..15d64eaea89f 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -277,6 +277,12 @@ clint: timer@ffdc000000 {
>                                               <&cpu3_intc 3>, <&cpu3_intc 7>;
>                 };
>
> +               rst_vi: reset-controller@ffe4040100 {
> +                       compatible = "thead,th1520-reset-vi";
> +                       reg = <0xff 0xe4040100 0x0 0x8>;
> +                       #reset-cells = <1>;
> +               };
> +
>                 spi0: spi@ffe700c000 {
>                         compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
>                         reg = <0xff 0xe700c000 0x0 0x1000>;
> @@ -502,6 +508,18 @@ uart2: serial@ffec010000 {
>                         status = "disabled";
>                 };
>
> +               rst_misc: reset-controller@ffec02c000 {
> +                       compatible = "thead,th1520-reset-misc";
> +                       reg = <0xff 0xec02c000 0x0 0x18>;
> +                       #reset-cells = <1>;
> +               };
> +
> +               rst_vp: reset-controller@ffecc30000 {
> +                       compatible = "thead,th1520-reset-vp";
> +                       reg = <0xff 0xecc30000 0x0 0x14>;
> +                       #reset-cells = <1>;
> +               };
> +
>                 clk: clock-controller@ffef010000 {
>                         compatible = "thead,th1520-clk-ap";
>                         reg = <0xff 0xef010000 0x0 0x1000>;
> @@ -509,6 +527,18 @@ clk: clock-controller@ffef010000 {
>                         #clock-cells = <1>;
>                 };
>
> +               rst_ap: reset-controller@ffef014000 {
> +                       compatible = "thead,th1520-reset-ap";
> +                       reg = <0xff 0xef014000 0x0 0x1000>;
> +                       #reset-cells = <1>;
> +               };
> +
> +               rst_dsp: reset-controller@ffef040028 {
> +                       compatible = "thead,th1520-reset-dsp";
> +                       reg = <0xff 0xef040028 0x0 0x4>;
> +                       #reset-cells = <1>;
> +               };
> +
>                 gpu: gpu@ffef400000 {
>                         compatible = "thead,th1520-gpu", "img,img-bxm-4-64",
>                                      "img,img-rogue";
> @@ -681,6 +711,13 @@ aogpio: gpio-controller@0 {
>                         };
>                 };
>
> +               rst_ao: reset-controller@fffff44000 {
> +                       compatible = "thead,th1520-reset-ao";
> +                       reg = <0xff 0xfff44000 0x0 0x2000>;
> +                       #reset-cells = <1>;
> +                       status = "reserved";
> +               };
> +
>                 padctrl_aosys: pinctrl@fffff4a000 {
>                         compatible = "thead,th1520-pinctrl";
>                         reg = <0xff 0xfff4a000 0x0 0x2000>;
> --
> 2.50.1
>
LGTM!

Acked-by: Guo Ren <guoren@kernel.org>

-- 
Best Regards
 Guo Ren

Re: [PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520

[Drew Fustini]

On Tue, Oct 14, 2025 at 01:10:32PM +0000, Yao Zi wrote:
> Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
> one for AO subsystem is marked as reserved, since it may be used by AON
> firmware.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index e680d1a7c821..15d64eaea89f 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -277,6 +277,12 @@ clint: timer@ffdc000000 {
>  					      <&cpu3_intc 3>, <&cpu3_intc 7>;
>  		};
>  
> +		rst_vi: reset-controller@ffe4040100 {
> +			compatible = "thead,th1520-reset-vi";
> +			reg = <0xff 0xe4040100 0x0 0x8>;

Is this intentional so that the first VI_SUBSYS register, VISYS_SW_RST
at offset 0x100, will have an offset of 0 from the thead,th1520-reset-vi
reg in the driver?

[snip]
> +		rst_dsp: reset-controller@ffef040028 {
> +			compatible = "thead,th1520-reset-dsp";
> +			reg = <0xff 0xef040028 0x0 0x4>;

Similar to rst_vi, is this intentional so that the first register,
DSPSYS_SW_RST at offset 0x28, will have an offset of 0 in the driver?

Thanks,
Drew

Re: [PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520

[Yao Zi]

On Mon, Oct 27, 2025 at 11:56:15AM +0000, Drew Fustini wrote:
> On Tue, Oct 14, 2025 at 01:10:32PM +0000, Yao Zi wrote:
> > Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
> > one for AO subsystem is marked as reserved, since it may be used by AON
> > firmware.
> > 
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> >  arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
> >  1 file changed, 37 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> > index e680d1a7c821..15d64eaea89f 100644
> > --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> > @@ -277,6 +277,12 @@ clint: timer@ffdc000000 {
> >  					      <&cpu3_intc 3>, <&cpu3_intc 7>;
> >  		};
> >  
> > +		rst_vi: reset-controller@ffe4040100 {
> > +			compatible = "thead,th1520-reset-vi";
> > +			reg = <0xff 0xe4040100 0x0 0x8>;
> 
> Is this intentional so that the first VI_SUBSYS register, VISYS_SW_RST
> at offset 0x100, will have an offset of 0 from the thead,th1520-reset-vi
> reg in the driver?

Yes, it's intentional for both VI and DSP subsystem. As you could see,
excluding these TEE-only shadows, the first reset-related register in
VI_SUBSYS is at offset 0x100. For DSP subsystem, it's at offset 0x28
(and is the only reset-related register).

I want to keep the first 0x100 bytes in VI_SUBSYS, and first 0x24 bytes
in DSP_SUBSYS free, because they're clock-related registers, and should
be reserved for clock driver introduced in the future.

In TH1520 SoC, only AON and AP subsystems have strictly separated reset
and clock register regions. For all other subsystems like VI, VO, VP,
MISC and DSP, reset and clock registers tightly follow each other, but
they don't interleave.

This series follows the way in which VO clock/reset controllers are
modeled in devicetree, where the subsystem region is split into two
nodes, one for clock and one for reset. This will lead to less regular
address/size values like what you noticed, as the registers do stay very
close.

> [snip]
> > +		rst_dsp: reset-controller@ffef040028 {
> > +			compatible = "thead,th1520-reset-dsp";
> > +			reg = <0xff 0xef040028 0x0 0x4>;
> 
> Similar to rst_vi, is this intentional so that the first register,
> DSPSYS_SW_RST at offset 0x28, will have an offset of 0 in the driver?
> 
> Thanks,
> Drew

Best regards,
Yao Zi

Re: [PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520

[Drew Fustini]

On Tue, Oct 14, 2025 at 01:10:32PM +0000, Yao Zi wrote:
> Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
> one for AO subsystem is marked as reserved, since it may be used by AON
> firmware.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)

Reviewed-by: Drew Fustini <fustini@kernel.org>

There is a conflict now in next but I will fix it when applying.

Thanks,
Drew

Re: [PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520

[Drew Fustini]

On Tue, Oct 14, 2025 at 01:10:32PM +0000, Yao Zi wrote:
> Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
> one for AO subsystem is marked as reserved, since it may be used by AON
> firmware.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)

I've applied this to thead-dt-for-next.

Thanks,
Drew

Re: [PATCH v3 0/5] Add reset controllers for other TH1520 subsystems

[Philipp Zabel]

On Di, 2025-10-14 at 13:10 +0000, Yao Zi wrote:
> TH1520 SoC is split into several subsystems, and each of them comes with
> distinct reset controllers. We've already had the one for VO subsystem
> documented as "thead,th1520-reset" and supported, and this series adds
> support for others, including AO, VI, MISC, AP, DSP and VO.
> 
> For TH1520_RESET_ID_{NPU,WDT0,WDT1}, these're reset signals that have
> been introduced along with support for the VO reset controller. However,
> registers in control of these resets don't stay in the VO reset region,
> instead they're AP-subsystem resets, thus the original ABI is
> problematic. I remove them in PATCH 1 and reintroduce them in PATCH 2.
[...]

Patches 1-4 applied to reset/next, thanks!

[1/5] dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets
      https://git.pengutronix.de/cgit/pza/linux/commit/?id=68ce5ac15ff8
[2/5] dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys
      https://git.pengutronix.de/cgit/pza/linux/commit/?id=76001d5d3cd1
[3/5] reset: th1520: Prepare for supporting multiple controllers
      https://git.pengutronix.de/cgit/pza/linux/commit/?id=ac3d323caee8
[4/5] reset: th1520: Support reset controllers in more subsystems
      https://git.pengutronix.de/cgit/pza/linux/commit/?id=f5da5084e282

regards
Philipp