From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5E4CE27FB3E for ; Mon, 3 Nov 2025 14:35:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762180520; cv=none; b=b2a9EksXbOo2kAbxB+YjtQs0gSsCpipYwplalfJuEB+PuCcvdTo5qDw2Sa6k5Ft3Ka84Jw9csJjTcTWGowNhY9GK18lQHzGpwnpBYLqsIrXIjO3t98JUj2xnGo5A13wtmYELCqmpRdzfODotg4b4ya8IGqkckTbeZynuLevMscM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762180520; c=relaxed/simple; bh=ahgrLHF7leplhOoUtDnHYXdpLuZRoQTXOFELYTXYe/U=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=MxMen4enSXe5gyUyeHzq3o93WKYDb73X82YKJfSCAKzPiibtVg9xDS8rzV/Hp8VBfoBQMOT0MgMYrYKwoCXbLJ5dWKpVPWsy1Vnxvo74NTkOuWctalimfB5zbp7VTHVp4yYLoXhSY2q+Lvfl6Cag1k7k3OOA/Mtyk5Zd7O92ZvA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B00641D14 for ; Mon, 3 Nov 2025 06:35:09 -0800 (PST) Received: from e110455-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 43DB03F694 for ; Mon, 3 Nov 2025 06:35:17 -0800 (PST) Date: Mon, 3 Nov 2025 14:34:51 +0000 From: Liviu Dudau To: Marek Vasut Cc: linux-arm-kernel@lists.infradead.org, Alexander Stein , Frank Li , "Rob Herring (Arm)" , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , "Jiyu Yang (OSS)" , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , Xianzhong Li , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: Re: [PATCH v4 1/2] dt-bindings: gpu: mali-valhall-csf: Document i.MX95 support Message-ID: References: <20251102160927.45157-1-marek.vasut@mailbox.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20251102160927.45157-1-marek.vasut@mailbox.org> On Sun, Nov 02, 2025 at 05:09:06PM +0100, Marek Vasut wrote: > The instance of the GPU populated in Freescale i.MX95 is the > Mali G310, document support for this variant. > > Reviewed-by: Alexander Stein > Reviewed-by: Frank Li > Reviewed-by: Rob Herring (Arm) > Signed-off-by: Marek Vasut I've pushed the series to drm-misc-next. Best regards, Liviu > --- > Cc: Boris Brezillon > Cc: Conor Dooley > Cc: David Airlie > Cc: Fabio Estevam > Cc: Jiyu Yang (OSS) > Cc: Krzysztof Kozlowski > Cc: Liviu Dudau > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Pengutronix Kernel Team > Cc: Philipp Zabel > Cc: Rob Herring > Cc: Sascha Hauer > Cc: Sebastian Reichel > Cc: Shawn Guo > Cc: Simona Vetter > Cc: Steven Price > Cc: Thomas Zimmermann > Cc: Xianzhong Li > Cc: devicetree@vger.kernel.org > Cc: dri-devel@lists.freedesktop.org > Cc: imx@lists.linux.dev > Cc: linux-arm-kernel@lists.infradead.org > --- > V2: - Add RB from Frank and Alexander > - Make resets: mandatory on i.MX95 > - Switch from fsl, to nxp, vendor prefix > V3: - Add RB from Rob > - Drop the reset part, this is now unnecessary > V4: - No change > --- > Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > index 613040fdb4448..8da8ceb0308d8 100644 > --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > @@ -19,6 +19,7 @@ properties: > - items: > - enum: > - mediatek,mt8196-mali > + - nxp,imx95-mali # G310 > - rockchip,rk3588-mali > - const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable > > -- > 2.51.0 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ¯\_(ツ)_/¯