* Re: [PATCH v3] arm64: tegra: Add pinctrl definitions for pcie-ep nodes
2025-10-09 14:22 [PATCH v3] arm64: tegra: Add pinctrl definitions for pcie-ep nodes Niklas Cassel
@ 2025-10-15 16:38 ` Manikanta Maddireddy
2025-11-04 14:53 ` Niklas Cassel
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Manikanta Maddireddy @ 2025-10-15 16:38 UTC (permalink / raw)
To: Niklas Cassel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Thierry Reding, Jonathan Hunter, Vidya Sagar, Vedant Deshpande
Cc: Shin'ichiro Kawasaki, Thierry Reding, devicetree, linux-tegra
Looks good to me
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
On 09/10/25 7:52 pm, Niklas Cassel wrote:
> External email: Use caution opening links or attachments
>
>
> When the PCIe controller is running in endpoint mode, the controller
> initialization is triggered by a PERST# (PCIe reset) GPIO deassertion.
>
> The driver has configured an IRQ to trigger when the PERST# GPIO changes
> state. Without the pinctrl definition, we do not get an IRQ when PERST#
> is deasserted, so the PCIe controller never gets initialized.
>
> Add the missing definitions, so that the controller actually gets
> initialized.
>
> Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
> Fixes: 0580286d0d22 ("arm64: tegra: Add Tegra234 PCIe C4 EP definition")
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
> Changes since v2:
> -Add pinctrl definitions to all pcie-ep nodes, not just C4 controller.
>
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 57 ++++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index df034dbb82853..cc929e1a00744 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -9,6 +9,7 @@
> #include <dt-bindings/power/tegra234-powergate.h>
> #include <dt-bindings/reset/tegra234-reset.h>
> #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
> +#include <dt-bindings/pinctrl/pinctrl-tegra.h>
>
> / {
> compatible = "nvidia,tegra234";
> @@ -127,6 +128,52 @@ gpio: gpio@2200000 {
> pinmux: pinmux@2430000 {
> compatible = "nvidia,tegra234-pinmux";
> reg = <0x0 0x2430000 0x0 0x19100>;
> +
> + pex_rst_c4_in_state: pinmux-pex-rst-c4-in {
> + pex_rst {
> + nvidia,pins = "pex_l4_rst_n_pl1";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + pex_rst_c5_in_state: pinmux-pex-rst-c5-in {
> + pex_rst {
> + nvidia,pins = "pex_l5_rst_n_paf1";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + pex_rst_c6_in_state: pinmux-pex-rst-c6-in {
> + pex_rst {
> + nvidia,pins = "pex_l6_rst_n_paf3";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + pex_rst_c7_in_state: pinmux-pex-rst-c7-in {
> + pex_rst {
> + nvidia,pins = "pex_l7_rst_n_pag1";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + pex_rst_c10_in_state: pinmux-pex-rst-c10-in {
> + pex_rst {
> + nvidia,pins = "pex_l10_rst_n_pag7";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> };
>
> gpcdma: dma-controller@2600000 {
> @@ -4630,6 +4677,8 @@ pcie-ep@140e0000 {
> <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c10_in_state>;
> interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
>
> @@ -4881,6 +4930,8 @@ pcie-ep@14160000 {
> <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c4_in_state>;
> interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
> nvidia,bpmp = <&bpmp 4>;
> @@ -5023,6 +5074,8 @@ pcie-ep@141a0000 {
> <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c5_in_state>;
> interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
>
> @@ -5115,6 +5168,8 @@ pcie-ep@141c0000 {
> <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c6_in_state>;
> interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
>
> @@ -5207,6 +5262,8 @@ pcie-ep@141e0000 {
> <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c7_in_state>;
> interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
>
> --
> 2.51.0
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v3] arm64: tegra: Add pinctrl definitions for pcie-ep nodes
2025-10-09 14:22 [PATCH v3] arm64: tegra: Add pinctrl definitions for pcie-ep nodes Niklas Cassel
2025-10-15 16:38 ` Manikanta Maddireddy
@ 2025-11-04 14:53 ` Niklas Cassel
2025-11-05 13:37 ` Thierry Reding
2025-11-05 14:04 ` Jon Hunter
3 siblings, 0 replies; 7+ messages in thread
From: Niklas Cassel @ 2025-11-04 14:53 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
Jonathan Hunter, Vidya Sagar, Vedant Deshpande
Cc: Shin'ichiro Kawasaki, Thierry Reding, devicetree, linux-tegra
On Thu, Oct 09, 2025 at 04:22:54PM +0200, Niklas Cassel wrote:
> When the PCIe controller is running in endpoint mode, the controller
> initialization is triggered by a PERST# (PCIe reset) GPIO deassertion.
>
> The driver has configured an IRQ to trigger when the PERST# GPIO changes
> state. Without the pinctrl definition, we do not get an IRQ when PERST#
> is deasserted, so the PCIe controller never gets initialized.
>
> Add the missing definitions, so that the controller actually gets
> initialized.
>
> Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
> Fixes: 0580286d0d22 ("arm64: tegra: Add Tegra234 PCIe C4 EP definition")
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
Gentle ping
Kind regards,
Niklas
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v3] arm64: tegra: Add pinctrl definitions for pcie-ep nodes
2025-10-09 14:22 [PATCH v3] arm64: tegra: Add pinctrl definitions for pcie-ep nodes Niklas Cassel
2025-10-15 16:38 ` Manikanta Maddireddy
2025-11-04 14:53 ` Niklas Cassel
@ 2025-11-05 13:37 ` Thierry Reding
2025-11-11 13:40 ` Niklas Cassel
2025-11-05 14:04 ` Jon Hunter
3 siblings, 1 reply; 7+ messages in thread
From: Thierry Reding @ 2025-11-05 13:37 UTC (permalink / raw)
To: Niklas Cassel
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jonathan Hunter,
Vidya Sagar, Vedant Deshpande, Shin'ichiro Kawasaki,
Thierry Reding, devicetree, linux-tegra
[-- Attachment #1: Type: text/plain, Size: 1082 bytes --]
On Thu, Oct 09, 2025 at 04:22:54PM +0200, Niklas Cassel wrote:
> When the PCIe controller is running in endpoint mode, the controller
> initialization is triggered by a PERST# (PCIe reset) GPIO deassertion.
>
> The driver has configured an IRQ to trigger when the PERST# GPIO changes
> state. Without the pinctrl definition, we do not get an IRQ when PERST#
> is deasserted, so the PCIe controller never gets initialized.
>
> Add the missing definitions, so that the controller actually gets
> initialized.
>
> Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
> Fixes: 0580286d0d22 ("arm64: tegra: Add Tegra234 PCIe C4 EP definition")
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
> Changes since v2:
> -Add pinctrl definitions to all pcie-ep nodes, not just C4 controller.
>
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 57 ++++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
Applied thanks. I did add blank lines between the blocks since that's
what I prefer. I hope you don't mind.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v3] arm64: tegra: Add pinctrl definitions for pcie-ep nodes
2025-11-05 13:37 ` Thierry Reding
@ 2025-11-11 13:40 ` Niklas Cassel
2025-11-11 16:37 ` Thierry Reding
0 siblings, 1 reply; 7+ messages in thread
From: Niklas Cassel @ 2025-11-11 13:40 UTC (permalink / raw)
To: Thierry Reding
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jonathan Hunter,
Vidya Sagar, Vedant Deshpande, Shin'ichiro Kawasaki,
Thierry Reding, devicetree, linux-tegra
On Wed, Nov 05, 2025 at 02:37:33PM +0100, Thierry Reding wrote:
> On Thu, Oct 09, 2025 at 04:22:54PM +0200, Niklas Cassel wrote:
> > When the PCIe controller is running in endpoint mode, the controller
> > initialization is triggered by a PERST# (PCIe reset) GPIO deassertion.
> >
> > The driver has configured an IRQ to trigger when the PERST# GPIO changes
> > state. Without the pinctrl definition, we do not get an IRQ when PERST#
> > is deasserted, so the PCIe controller never gets initialized.
> >
> > Add the missing definitions, so that the controller actually gets
> > initialized.
> >
> > Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
> > Fixes: 0580286d0d22 ("arm64: tegra: Add Tegra234 PCIe C4 EP definition")
> > Signed-off-by: Niklas Cassel <cassel@kernel.org>
> > ---
> > Changes since v2:
> > -Add pinctrl definitions to all pcie-ep nodes, not just C4 controller.
> >
> > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 57 ++++++++++++++++++++++++
> > 1 file changed, 57 insertions(+)
>
> Applied thanks. I did add blank lines between the blocks since that's
> what I prefer. I hope you don't mind.
Perfectly fine with me, you are the maintainer :)
However, I don't see this patch queued on any branch @
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git/
Did you perhaps forget to push?
Kind regards,
Niklas
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v3] arm64: tegra: Add pinctrl definitions for pcie-ep nodes
2025-11-11 13:40 ` Niklas Cassel
@ 2025-11-11 16:37 ` Thierry Reding
0 siblings, 0 replies; 7+ messages in thread
From: Thierry Reding @ 2025-11-11 16:37 UTC (permalink / raw)
To: Niklas Cassel
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jonathan Hunter,
Vidya Sagar, Vedant Deshpande, Shin'ichiro Kawasaki,
Thierry Reding, devicetree, linux-tegra
[-- Attachment #1: Type: text/plain, Size: 1701 bytes --]
On Tue, Nov 11, 2025 at 02:40:25PM +0100, Niklas Cassel wrote:
> On Wed, Nov 05, 2025 at 02:37:33PM +0100, Thierry Reding wrote:
> > On Thu, Oct 09, 2025 at 04:22:54PM +0200, Niklas Cassel wrote:
> > > When the PCIe controller is running in endpoint mode, the controller
> > > initialization is triggered by a PERST# (PCIe reset) GPIO deassertion.
> > >
> > > The driver has configured an IRQ to trigger when the PERST# GPIO changes
> > > state. Without the pinctrl definition, we do not get an IRQ when PERST#
> > > is deasserted, so the PCIe controller never gets initialized.
> > >
> > > Add the missing definitions, so that the controller actually gets
> > > initialized.
> > >
> > > Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
> > > Fixes: 0580286d0d22 ("arm64: tegra: Add Tegra234 PCIe C4 EP definition")
> > > Signed-off-by: Niklas Cassel <cassel@kernel.org>
> > > ---
> > > Changes since v2:
> > > -Add pinctrl definitions to all pcie-ep nodes, not just C4 controller.
> > >
> > > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 57 ++++++++++++++++++++++++
> > > 1 file changed, 57 insertions(+)
> >
> > Applied thanks. I did add blank lines between the blocks since that's
> > what I prefer. I hope you don't mind.
>
> Perfectly fine with me, you are the maintainer :)
>
> However, I don't see this patch queued on any branch @
> https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git/
>
> Did you perhaps forget to push?
Yes, of course I did. =) I was waiting for feedback on a quick patch I
added to the branch and then forgot to push out. Should all be up-to-
date now on kernel.org.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] arm64: tegra: Add pinctrl definitions for pcie-ep nodes
2025-10-09 14:22 [PATCH v3] arm64: tegra: Add pinctrl definitions for pcie-ep nodes Niklas Cassel
` (2 preceding siblings ...)
2025-11-05 13:37 ` Thierry Reding
@ 2025-11-05 14:04 ` Jon Hunter
3 siblings, 0 replies; 7+ messages in thread
From: Jon Hunter @ 2025-11-05 14:04 UTC (permalink / raw)
To: Niklas Cassel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Thierry Reding, Vidya Sagar, Vedant Deshpande
Cc: Shin'ichiro Kawasaki, Thierry Reding, devicetree, linux-tegra
On 09/10/2025 15:22, Niklas Cassel wrote:
> When the PCIe controller is running in endpoint mode, the controller
> initialization is triggered by a PERST# (PCIe reset) GPIO deassertion.
>
> The driver has configured an IRQ to trigger when the PERST# GPIO changes
> state. Without the pinctrl definition, we do not get an IRQ when PERST#
> is deasserted, so the PCIe controller never gets initialized.
>
> Add the missing definitions, so that the controller actually gets
> initialized.
>
> Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
> Fixes: 0580286d0d22 ("arm64: tegra: Add Tegra234 PCIe C4 EP definition")
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
> Changes since v2:
> -Add pinctrl definitions to all pcie-ep nodes, not just C4 controller.
>
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 57 ++++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index df034dbb82853..cc929e1a00744 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -9,6 +9,7 @@
> #include <dt-bindings/power/tegra234-powergate.h>
> #include <dt-bindings/reset/tegra234-reset.h>
> #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
> +#include <dt-bindings/pinctrl/pinctrl-tegra.h>
>
> / {
> compatible = "nvidia,tegra234";
> @@ -127,6 +128,52 @@ gpio: gpio@2200000 {
> pinmux: pinmux@2430000 {
> compatible = "nvidia,tegra234-pinmux";
> reg = <0x0 0x2430000 0x0 0x19100>;
> +
> + pex_rst_c4_in_state: pinmux-pex-rst-c4-in {
> + pex_rst {
> + nvidia,pins = "pex_l4_rst_n_pl1";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + pex_rst_c5_in_state: pinmux-pex-rst-c5-in {
> + pex_rst {
> + nvidia,pins = "pex_l5_rst_n_paf1";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + pex_rst_c6_in_state: pinmux-pex-rst-c6-in {
> + pex_rst {
> + nvidia,pins = "pex_l6_rst_n_paf3";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + pex_rst_c7_in_state: pinmux-pex-rst-c7-in {
> + pex_rst {
> + nvidia,pins = "pex_l7_rst_n_pag1";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + pex_rst_c10_in_state: pinmux-pex-rst-c10-in {
> + pex_rst {
> + nvidia,pins = "pex_l10_rst_n_pag7";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> };
>
> gpcdma: dma-controller@2600000 {
> @@ -4630,6 +4677,8 @@ pcie-ep@140e0000 {
> <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c10_in_state>;
> interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
>
> @@ -4881,6 +4930,8 @@ pcie-ep@14160000 {
> <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c4_in_state>;
> interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
> nvidia,bpmp = <&bpmp 4>;
> @@ -5023,6 +5074,8 @@ pcie-ep@141a0000 {
> <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c5_in_state>;
> interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
>
> @@ -5115,6 +5168,8 @@ pcie-ep@141c0000 {
> <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c6_in_state>;
> interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
>
> @@ -5207,6 +5262,8 @@ pcie-ep@141e0000 {
> <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
> reset-names = "apb", "core";
>
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c7_in_state>;
> interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> interrupt-names = "intr";
>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Thanks!
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 7+ messages in thread