Re: [PATCH net-next 2/2] net: pcs: rzn1-miic: Add support for PHY link active-level configuration

["Russell King (Oracle)" <linux@armlinux.org.uk>]

On Wed, Nov 12, 2025 at 08:19:37PM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add support to configure the PHY link signal active level per converter
> using the DT property "renesas,miic-phylink-active-low".
> 
> Introduce the MIIC_PHYLINK register definition and extend the MIIC driver
> with a new `phylink` structure to store the mask and value for PHY link
> configuration. Implement `miic_configure_phylink()` to determine the bit
> position and polarity for each port based on the SoC type, such as RZ/N1
> or RZ/T2H/N2H.

To echo what Andrew said... really really bad naming.

include/linux/phylink.h:struct phylink;

This structure identifier is already in use, and what's more, this
driver includes that header file.

What exactly is this "PHY link signal" that you talk about in the
commit description? Apart from the LED outputs, I'm not aware of
generally PHYs having a hardware output to indicate link status.

If we're talking about the link status bit in the SGMII config
word, if there's PHYs that have that bit inverted, they deserve to
be broken, because they will be broken with most hardware that
interprets the link state bit (I've never seen the facility to
invert that bit in hardware.)

Basically, please explain what this is for, what this is doing, and
why it is necessary.

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