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Thu, 13 Nov 2025 20:41:53 -0800 (PST) Date: Fri, 14 Nov 2025 01:41:46 -0300 From: Geraldo Nascimento To: =?utf-8?B?5byg54Oo?= Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci , linux-arm-kernel , linux-kernel , devicetree , krzk+dt , conor+dt , Johan Jonker , linux-rockchip , Simon Glass , Philipp Tomsich , Kever Yang , Tom Rini , u-boot@lists.denx.de Subject: Re: [PATCH] arm64: dts: rockchip: align bindings to PCIe spec Message-ID: References: <4b5ffcccfef2a61838aa563521672a171acb27b2.1762321976.git.geraldogabriel@gmail.com> <67b605b0-7046-448a-bc9b-d3ac56333809@rock-chips.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Nov 12, 2025 at 10:09:15PM -0300, Geraldo Nascimento wrote: > Hi Ye, Shawn, > > Here's more contained workaround without resorting to clearing DDR to > INPUT for every GPIO: > > diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c > index ee1822ca01db..1d89131ec6ac 100644 > --- a/drivers/pci/controller/pcie-rockchip-host.c > +++ b/drivers/pci/controller/pcie-rockchip-host.c > @@ -315,7 +315,8 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) > PCIE_CLIENT_CONFIG); > > msleep(PCIE_T_PVPERL_MS); > - gpiod_set_value_cansleep(rockchip->perst_gpio, 1); > + gpiod_direction_input(rockchip->perst_gpio); > + gpiod_direction_output(rockchip->perst_gpio, 1); > > msleep(PCIE_RESET_CONFIG_WAIT_MS); > > This results in working PCIe for me, pass initial link training. Sorry for the inconvenience of more mail, but I'm providing as much detail as I can. This hack has been confirmed to work in U-boot also. diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c index 19f9e58a640..5702b607ee6 100644 --- a/drivers/pci/pcie_rockchip.c +++ b/drivers/pci/pcie_rockchip.c @@ -329,8 +329,10 @@ static int rockchip_pcie_init_port(struct udevice *dev) writel(PCIE_CLIENT_LINK_TRAIN_ENABLE, priv->apb_base + PCIE_CLIENT_CONFIG); - if (dm_gpio_is_valid(&priv->ep_gpio)) - dm_gpio_set_value(&priv->ep_gpio, 1); + if (dm_gpio_is_valid(&priv->ep_gpio)) { + dm_gpio_set_dir_flags(&priv->ep_gpio, (priv->ep_gpio.flags & ~GPIOD_IS_OUT) | GPIOD_IS_IN); + dm_gpio_set_dir_flags(&priv->ep_gpio, (priv->ep_gpio.flags & ~GPIOD_IS_IN) | GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + } ret = readl_poll_sleep_timeout (priv->apb_base + PCIE_CLIENT_BASIC_STATUS1, So my report suggests this is not specific to Linux and because same workaround works in U-boot simplified driver model I suggest you check from your side. Previously PCIe link training timeout, not working. Now I'm very happy with working PCIe in Linux and U-boot. Thanks, Geraldo Nascimento