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Sat, 15 Nov 2025 01:49:40 -0800 (PST) Date: Sat, 15 Nov 2025 06:49:33 -0300 From: Geraldo Nascimento To: Dragan Simic Cc: linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Conor Dooley , Johan Jonker Subject: Re: [PATCH 1/3] PCI: rockchip: warn of danger of 5.0 GT/s speeds Message-ID: References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Sat, Nov 15, 2025 at 10:24:49AM +0100, Dragan Simic wrote: > Hello Geraldo, > > On Saturday, November 15, 2025 10:10 CET, Geraldo Nascimento wrote: > > Shawn Lin from Rockchip has reiterated that there may be danger in using > > their PCIe with 5.0 GT/s speeds. Warn the user if they make a DT change > > from the default and at the same time, drive at 2.5 GT/s only, in case > > the DT max-link-speed property is invalid or inexistent. > > > > Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver") > > Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/ > > Reported-by: Shawn Lin > > Signed-off-by: Geraldo Nascimento > > --- > > drivers/pci/controller/pcie-rockchip.c | 8 ++++++-- > > 1 file changed, 6 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > > index 0f88da378805..ed67886a6d43 100644 > > --- a/drivers/pci/controller/pcie-rockchip.c > > +++ b/drivers/pci/controller/pcie-rockchip.c > > @@ -66,8 +66,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) > > } > > > > rockchip->link_gen = of_pci_get_max_link_speed(node); > > - if (rockchip->link_gen < 0 || rockchip->link_gen > 2) > > - rockchip->link_gen = 2; > > + if (rockchip->link_gen < 0 || rockchip->link_gen > 2) { > > + rockchip->link_gen = 1; > > + dev_warn(dev, "invalid max-link-speed, set to 2.5 GT/s\n"); > > + } > > + else if (rockchip->link_gen == 2) > > + dev_warn(dev, "5.0 GT/s may lead to catastrophic failure\n"); > > > > for (i = 0; i < ROCKCHIP_NUM_PM_RSTS; i++) > > rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i]; > > Looking good to me, thanks for this patch! People often declare > PCIe Gen2 on RK3399-based boards as "works for me", which actually > happens very often, but such simple evaluations cannot be taken > as a proof of Gen2 correctness. > > Furthermore, RK3399's internal interconnects limit the effective > I/O speed of PCIe transfers already, so switching to PCIe Gen1 > actually doesn't result in some large I/O performance penalties. > > With all that in mind, please feel free to include > > Reviewed-by: Dragan Simic Hi Dragan, I think I'll include a Reported-By: you too, since you were the first to warn me of unknown errata regarding Rockchip PCIe. I told you it was a test of mine but I didn't realize the grave danger implied by Shawn Lin declarations. Once I realized this could end badly the only way I could retribute was to send a few corrections :) Thank you, Geraldo Nascimento