From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m16.yeah.net (mail-m16.yeah.net [1.95.21.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64EA222256F for ; Sun, 16 Nov 2025 12:22:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=1.95.21.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763295765; cv=none; b=jvA7Qma3k0uA4SwoOWJ2IwiTimbNvnxrfPSOfLKgXv/tA8jO+aFGo75WQzI4iKwHEODJo0UK8HmrJc2TtwrSWLzjabOd0kpZarFOEgOvFGMohwbwXjIftb1as5mW/vDVTSnvG3LP294SkY61sizmr+AT8DsIXVPxrpzaL3c9Axg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763295765; c=relaxed/simple; bh=1cLquhH65JzfLpgnxTzIzOT+49biTP7PD3iQcNve5iQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=jynLyMEoqltQYC1HEDIKrU/NBZPf+DUvJtzpd4p3E1EmzRnzLjDuTejXpj+kKpG9qzS2m3ehanp36jC6vQPoL5nldqoUrL4X5FJ1AbbC6CYzeRnYL5/sAzacgNFLxRsDHm42Uw93K3TqcqRjBYB/1KJ1pOniiRaASSVfaZvS718= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=yeah.net; spf=pass smtp.mailfrom=yeah.net; dkim=pass (1024-bit key) header.d=yeah.net header.i=@yeah.net header.b=R5MLfLFN; arc=none smtp.client-ip=1.95.21.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=yeah.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=yeah.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=yeah.net header.i=@yeah.net header.b="R5MLfLFN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yeah.net; s=s110527; h=Date:From:To:Subject:Message-ID:MIME-Version: Content-Type; bh=kNW9yPvfa/OhtLEXuIIfofqtoj6rCxgnTJJKlGU6kjg=; b=R5MLfLFNkagzbrOgQ/NYPkwh/zPPi+ubMxzJRVvX1yodJ1sL4JADl7W+HZ0GLJ TEOFiOBFgSX/FsUiIrUGTd6BZZfK6c1BZU67zka7J3TcoeMBtNQFVEO9/z3RPJUt qp92xrqBT0erQuFQn6s5qd5RkZYGSBKYu4nF9f5cT6y2A= Received: from dragon (unknown []) by gzsmtp1 (Coremail) with SMTP id Mc8vCgAXXyeqwRlpCI87AQ--.8095S3; Sun, 16 Nov 2025 20:21:01 +0800 (CST) Date: Sun, 16 Nov 2025 20:20:58 +0800 From: Shawn Guo To: Marek Vasut Cc: linux-arm-kernel@lists.infradead.org, Frank Li , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , "Jiyu Yang (OSS)" , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , Xianzhong Li , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: Re: [PATCH v4 2/2] arm64: dts: imx95: Describe Mali G310 GPU Message-ID: References: <20251102160927.45157-1-marek.vasut@mailbox.org> <20251102160927.45157-2-marek.vasut@mailbox.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251102160927.45157-2-marek.vasut@mailbox.org> X-CM-TRANSID:Mc8vCgAXXyeqwRlpCI87AQ--.8095S3 X-Coremail-Antispam: 1Uf129KBjvJXoWxZr1UGFW8KF43Ww1xZF1rCrg_yoWrJryDpr WDCw45Cr4kXr1Ik3WagFW0ka4fuw4kCFyUur1DG3yjyry2qryIqFnIkrnaga4UXF1UGa1U trnFqryI9wnxu3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07U9iSdUUUUU= X-CM-SenderInfo: pvkd40hjxrjqh1hdxhhqhw/1tbiNw48oWkZwa5RngAA30 On Sun, Nov 02, 2025 at 05:09:07PM +0100, Marek Vasut wrote: > The instance of the GPU populated in i.MX95 is the G310, describe this > GPU in the DT. Include dummy GPU voltage regulator and OPP tables. The commit log seems need an update for the regulator part? Shawn > > Reviewed-by: Frank Li > Signed-off-by: Marek Vasut > --- > Cc: Boris Brezillon > Cc: Conor Dooley > Cc: David Airlie > Cc: Fabio Estevam > Cc: Jiyu Yang (OSS) > Cc: Krzysztof Kozlowski > Cc: Liviu Dudau > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Pengutronix Kernel Team > Cc: Philipp Zabel > Cc: Rob Herring > Cc: Sascha Hauer > Cc: Sebastian Reichel > Cc: Shawn Guo > Cc: Simona Vetter > Cc: Steven Price > Cc: Thomas Zimmermann > Cc: Xianzhong Li > Cc: devicetree@vger.kernel.org > Cc: dri-devel@lists.freedesktop.org > Cc: imx@lists.linux.dev > Cc: linux-arm-kernel@lists.infradead.org > --- > V2: - Drop regulator-{always,boot}-on from fixed-gpu-reg regulator > - Keep the GPU and GPUMIX always enabled > - Switch from fsl, to nxp, vendor prefix > - Fix opp_table to opp-table > - Describe IMX95_CLK_GPUAPB as coregroup clock > - Sort interrupts by their names to match bindings > V3: - Drop perf power domain > - Drop reset block controller > V4: - Add RB from Frank > - Drop the now optional GPU regulator > --- > arch/arm64/boot/dts/freescale/imx95.dtsi | 37 ++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi > index a91e1724ab1a4..e45014d50abef 100644 > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi > @@ -250,6 +250,28 @@ dummy: clock-dummy { > clock-output-names = "dummy"; > }; > > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + opp-hz-real = /bits/ 64 <500000000>; > + opp-microvolt = <920000>; > + }; > + > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-hz-real = /bits/ 64 <800000000>; > + opp-microvolt = <920000>; > + }; > + > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-hz-real = /bits/ 64 <1000000000>; > + opp-microvolt = <920000>; > + }; > + }; > + > clk_ext1: clock-ext1 { > compatible = "fixed-clock"; > #clock-cells = <0>; > @@ -2139,6 +2161,21 @@ netc_emdio: mdio@0,0 { > }; > }; > > + gpu: gpu@4d900000 { > + compatible = "nxp,imx95-mali", "arm,mali-valhall-csf"; > + reg = <0 0x4d900000 0 0x480000>; > + clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>; > + clock-names = "core", "coregroup"; > + interrupts = , > + , > + ; > + interrupt-names = "job", "mmu", "gpu"; > + operating-points-v2 = <&gpu_opp_table>; > + power-domains = <&scmi_devpd IMX95_PD_GPU>; > + #cooling-cells = <2>; > + dynamic-power-coefficient = <1013>; > + }; > + > ddr-pmu@4e090dc0 { > compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; > reg = <0x0 0x4e090dc0 0x0 0x200>; > -- > 2.51.0 >