Re: [PATCH 10/22] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC

[Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>]

Hi Krzysztof,
Thanks for your review!

On Wed, Dec 03, 2025 at 09:23:53AM +0100, Krzysztof Kozlowski wrote:
> On Wed, Nov 26, 2025 at 03:07:22PM +0100, Tommaso Merciai wrote:
> > The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> > Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> > Processor (VSPD), and Display Unit (DU).
> > 
> >  - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> >  - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> > 
> > Add then two new SoC-specific compatible strings 'renesas,r9a09g047-du0'
> > and 'renesas,r9a09g047-du1'.
> 
> LCDC0/1 but compatibles du0/du1...
> 
> What are the differences between DU0 and DU1? Just different outputs? Is
> the programming model the same?

The hardware configurations are different: these are two distinct hardware blocks.

Based on the block diagrams shown in Figures 9.4-2 (LCDC1) and 9.4-1 (LCDC0),
the only difference concerns the output, but this variation is internal to the
hardware blocks themselves.
Therefore, LCDC0 and LCDC1 are not identical blocks, and their programming models
differ as a result.

In summary, although most of the internal functions are the same, the two blocks
have output signals connected to different components within the SoC.
This requires different hardware configurations and inevitably leads to different
programming models for LCDC0 and LCDC1.


Kind Regards,
Tommaso


> 
> Best regards,
> Krzysztof
>