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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8899ea36210sm85899146d6.27.2025.12.16.18.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Dec 2025 18:46:01 -0800 (PST) Date: Wed, 17 Dec 2025 10:45:50 +0800 From: yuanjiey To: Dmitry Baryshkov Cc: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, yongxing.mou@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com Subject: Re: [PATCH v3 10/11] drm/msm/dpu: Refactor SSPP to compatible DPU 13.0.0 Message-ID: References: <20251215083854.577-1-yuanjie.yang@oss.qualcomm.com> <20251215083854.577-11-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE3MDAyMSBTYWx0ZWRfXybaCwV4WftBk RuLs75E5IqgzwtFdUuaioVxBfETr3Oqn30KpZpkERdqfhPtA4gGfcE/VofvxCNgtM0ZpSt6U9FD qClApjp1Vhu/0zVM0cchXZxrd97Di79vkuF34efhGLg0rk0irpIApY9qcD/C9Iou50VOnffa9zn YFCYgAAiiw7KlJdkL5llUQfjq7IS3uPpyG4Ze6tmmI7JutOYMEwSKML9FNI8btxks4qbTZKB22o tJlzBTH3qCvDLJ7qWItiu8JWGet0viaoy//JBZXLa9R4rRVYwOu6ZTnVz7vqudjrbY7wAtqzD+Q jIqzMZoOjdqsD9FvU4DO9WrV4oC6M1wnrzas0Tl0PY/9f1pOEPUgO9GXnX48cVHERQQkdd/dAIZ rEpFYJN8PS6d3AMJXFUKpRlFkO0QaQ== X-Proofpoint-ORIG-GUID: XdMVHMqJba_jMov2ews72PpJ-X9V1_M2 X-Proofpoint-GUID: XdMVHMqJba_jMov2ews72PpJ-X9V1_M2 X-Authority-Analysis: v=2.4 cv=edgwvrEH c=1 sm=1 tr=0 ts=6942196c cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=kj9zAlcOel0A:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=tNEIORBzTMdH9SYpPiUA:9 a=CjuIK1q_8ugA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-16_03,2025-12-16_05,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 adultscore=0 priorityscore=1501 phishscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512170021 On Tue, Dec 16, 2025 at 04:22:32PM +0200, Dmitry Baryshkov wrote: > On Tue, Dec 16, 2025 at 02:56:31PM +0800, yuanjiey wrote: > > On Mon, Dec 15, 2025 at 10:08:22PM +0200, Dmitry Baryshkov wrote: > > > On Mon, Dec 15, 2025 at 04:38:53PM +0800, yuanjie yang wrote: > > > > From: Yuanjie Yang > > > > > > > > DPU version 13.0.0 introduces structural changes including > > > > register additions, removals, and relocations. > > > > > > > > Refactor SSPP-related code to be compatible with DPU 13.0.0 > > > > modifications. > > > > > > > > Co-developed-by: Yongxing Mou > > > > Signed-off-by: Yongxing Mou > > > > Signed-off-by: Yuanjie Yang > > > > --- > > > > > > We've fixed the order of the interrupts patch. Now you are adding SSPP > > > customization for 13.x _after_ adding the first 13.x support. Is that > > > supposed to work? > > > > Yes, will reorganize order. > > And after comparing with v2, I'm really surprised. It was better before > and then you changed the order of the patches. Why? You were asked to > split it, but not to move it to the end. I make the mistake. Sure, I will keep the v2 patch order in next patch. > > > > > > > > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 15 +- > > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 155 ++++++++++-------- > > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 52 ++++++ > > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 ++ > > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 + > > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +- > > > > 6 files changed, 191 insertions(+), 69 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > > > > switch (ctx->ubwc->ubwc_enc_version) { > > > > case UBWC_1_0: > > > > fast_clear = fmt->alpha_enable ? BIT(31) : 0; > > > > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, > > > > - fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | > > > > - BIT(8) | > > > > - (ctx->ubwc->highest_bank_bit << 4)); > > > > + DPU_REG_WRITE(c, ubwc_ctrl_off, > > > > + fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | > > > > + BIT(8) | > > > > + (ctx->ubwc->highest_bank_bit << 4)); > > > > > > I have asked to drop unrelated changes. You didn't. Why? You are > > > changing whitespaces for no reason. It's just a noise which hides the > > > actual change here. > > > > here ubwc reg layout change in DPU 13. > > > > ubwc_ctrl_off > > veriosn < 13 > > reg: SSPP_UBWC_STATIC_CTRL > > verison >= 13 > > reg: SSPP_REC_UBWC_STATIC_CTRL > > > > So I do some fix. > > What does it have to do with the whitespaces? Fix _one_ line. get it, will drop unrelated whitespaces. > > > > > > break; > > > > case UBWC_2_0: > > > > fast_clear = fmt->alpha_enable ? BIT(31) : 0; > > > > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, > > > > - fast_clear | (ctx->ubwc->ubwc_swizzle) | > > > > - (ctx->ubwc->highest_bank_bit << 4)); > > > > + DPU_REG_WRITE(c, ubwc_ctrl_off, > > > > + fast_clear | (ctx->ubwc->ubwc_swizzle) | > > > > + (ctx->ubwc->highest_bank_bit << 4)); > > > > break; > > > > case UBWC_3_0: > > > > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, > > > > - BIT(30) | (ctx->ubwc->ubwc_swizzle) | > > > > - (ctx->ubwc->highest_bank_bit << 4)); > > > > + DPU_REG_WRITE(c, ubwc_ctrl_off, > > > > + BIT(30) | (ctx->ubwc->ubwc_swizzle) | > > > > + (ctx->ubwc->highest_bank_bit << 4)); > > > > break; > > > > case UBWC_4_0: > > > > - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, > > > > - MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); > > > > + DPU_REG_WRITE(c, ubwc_ctrl_off, > > > > + MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); > > > > break; > > > > } > > > > } > > > > @@ -313,19 +337,18 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, > > > > > > > > /* update scaler opmode, if appropriate */ > > > > if (test_bit(DPU_SSPP_CSC, &ctx->cap->features)) > > > > - _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, > > > > - MSM_FORMAT_IS_YUV(fmt)); > > > > + dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, > > > > + MSM_FORMAT_IS_YUV(fmt)); > > > > else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) > > > > - _sspp_setup_csc10_opmode(ctx, > > > > - VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, > > > > - MSM_FORMAT_IS_YUV(fmt)); > > > > + dpu_hw_sspp_setup_csc10_opmode(ctx, > > > > + VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, > > > > + MSM_FORMAT_IS_YUV(fmt)); > > > > > > Again, useless whitespace changes. > > checkpatch.pl says here is alignment issuse, so I do this fix. > > The issue was present before your patch. If you want to fix it, fix it > in the separate patch or ignore it. get it, will drop unrelated whitespaces. > > > > > > > > > > DPU_REG_WRITE(c, format_off, src_format); > > > > DPU_REG_WRITE(c, unpack_pat_off, unpack); > > > > DPU_REG_WRITE(c, op_mode_off, opmode); > > > > - > > > > > > Why? > > > > yes, will drop "-" diff. > > > > > > /* clear previous UBWC error */ > > > > - DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31)); > > > > + DPU_REG_WRITE(c, ubwc_err_off, BIT(31)); > > > > } > > > > > > > > static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, > > > > @@ -385,9 +408,9 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, > > > > tot_req_pixels[3]); > > > > } > > > > > > > > -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, > > > > - struct dpu_hw_scaler3_cfg *scaler3_cfg, > > > > - const struct msm_format *format) > > > > +void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, > > > > + struct dpu_hw_scaler3_cfg *scaler3_cfg, > > > > + const struct msm_format *format) > > > > > > And here... > > checkpatch.pl says here is alignment issuse, so I do this fix. > > And I'm asking you to don't do it. Don't clutter the patch with > unrelated changes (and whitespace / alignment changes are generally > unrelated). > > -- > With best wishes > Dmitry Thanks, Yuanjie