From: Inochi Amaoto <inochiama@gmail.com>
To: Troy Mitchell <troy.mitchell@linux.spacemit.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@gentoo.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Linus Walleij <linusw@kernel.org>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
spacemit@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-gpio@vger.kernel.org
Subject: Re: [PATCH 2/2] pinctrl: spacemit: support I/O power domain configuration
Date: Tue, 23 Dec 2025 17:42:26 +0800 [thread overview]
Message-ID: <aUpirQFWf3w-5PQ2@inochi.infowork> (raw)
In-Reply-To: <20251223-kx-pinctrl-aib-io-pwr-domain-v1-2-5f1090a487c7@linux.spacemit.com>
On Tue, Dec 23, 2025 at 05:11:12PM +0800, Troy Mitchell wrote:
> IO domain power control registers are used to configure the operating
> voltage of dual-voltage GPIO banks. By default, these registers are
> configured for 3.3V operation. As a result, even when a GPIO bank is
> externally supplied with 1.8V, the internal logic continues to
> operate in the 3.3V domain, which may lead to functional failures.
>
> This patch adds support for programming the IO domain power control
> registers, allowing dual-voltage GPIO banks to be explicitly configured
> for 1.8V operation when required.
>
> Care must be taken when configuring these registers. If a GPIO bank is
> externally supplied with 3.3V while the corresponding IO power domain
> is configured for 1.8V, external current injection (back-powering)
> may occur, potentially causing damage to the GPIO pin.
>
> Due to these hardware constraints and safety considerations, the IO
> domain power control registers are implemented as secure registers.
> Access to these registers requires unlocking via the AIB Secure Access
> Register (ASAR) in the APBC block before a single read or write
> operation can be performed.
>
> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
> ---
> arch/riscv/boot/dts/spacemit/k1.dtsi | 4 +-
> drivers/pinctrl/spacemit/pinctrl-k1.c | 131 +++++++++++++++++++++++++++++++++-
> 2 files changed, 131 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index 7818ca4979b6a7755722919a5958512aa11950ab..23ecb19624f227f3c39de35bf3078379f7a2490e 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -565,10 +565,12 @@ i2c8: i2c@d401d800 {
>
> pinctrl: pinctrl@d401e000 {
> compatible = "spacemit,k1-pinctrl";
> - reg = <0x0 0xd401e000 0x0 0x400>;
> + reg = <0x0 0xd401e000 0x0 0x400>,
> + <0x0 0xd401e800 0x0 0x34>;
> clocks = <&syscon_apbc CLK_AIB>,
> <&syscon_apbc CLK_AIB_BUS>;
> clock-names = "func", "bus";
> + spacemit,apbc = <&syscon_apbc 0x50>;
> };
This change breaks binding, can we use something like <0x0 0xd401e000 0x0 0x1000>?
If you insist on a new reg field, you should change the binding as well.
Regards,
Inochi
next prev parent reply other threads:[~2025-12-23 9:43 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-23 9:11 [PATCH 0/2] pinctrl: spacemit: support I/O power domain configuration Troy Mitchell
2025-12-23 9:11 ` [PATCH 1/2] dt-bindings: pinctrl: add syscon property Troy Mitchell
2025-12-27 12:58 ` Krzysztof Kozlowski
2025-12-27 12:58 ` Krzysztof Kozlowski
2026-01-01 22:54 ` Linus Walleij
2025-12-23 9:11 ` [PATCH 2/2] pinctrl: spacemit: support I/O power domain configuration Troy Mitchell
2025-12-23 9:32 ` Yixun Lan
2025-12-23 9:42 ` Troy Mitchell
2026-01-01 22:58 ` Linus Walleij
2025-12-23 9:42 ` Inochi Amaoto [this message]
2025-12-23 9:50 ` Troy Mitchell
2025-12-23 13:03 ` Yao Zi
2025-12-25 7:07 ` Troy Mitchell
2025-12-27 13:00 ` Krzysztof Kozlowski
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