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Thu, 08 Jan 2026 04:28:05 -0800 (PST) Date: Thu, 8 Jan 2026 09:29:52 -0300 From: Marcelo Schmitt To: David Lechner Cc: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , Nuno =?iso-8859-1?Q?S=E1?= , Jonathan Cameron , Andy Shevchenko , Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Subject: Re: [PATCH v4 2/9] spi: dt-bindings: add spi-{tx,rx}-lane-map properties Message-ID: References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> <20251219-spi-add-multi-bus-support-v4-2-145dc5204cd8@baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251219-spi-add-multi-bus-support-v4-2-145dc5204cd8@baylibre.com> On 12/19, David Lechner wrote: > Add spi-tx-lane-map and spi-rx-lane-map properties to the SPI peripheral > device tree binding. These properties allow specifying the mapping of > peripheral data lanes to controller data lanes. This is needed e.g. when > some lanes are skipped on the controller side so that the controller > can correctly route data to/from the peripheral. > > Signed-off-by: David Lechner > --- > > v4 changes: > - This replaces the data-lanes property from the previous revision. Now > there are separate properties for tx and rx lane maps. And instead of > being the primary property for determining the number of lanes, this > is only needed in special cases where the mapping is non-trivial. > --- > .../devicetree/bindings/spi/spi-peripheral-props.yaml | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml > index 59ddead7da14..2f278f145f78 100644 > --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml > +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml > @@ -75,6 +75,13 @@ properties: > enum: [0, 1, 2, 4, 8] > default: [1] > > + spi-rx-lane-map: > + description: Mapping of peripheral RX lanes to controller RX lanes. > + Each index in the array represents a peripheral RX lane, and the value > + at that index represents the corresponding controller RX lane. These are peripheral props so I guess RX is from peripheral perspective. In that case, those would be routed to controller TX lanes, no? Could maybe use MISO/MOSI or COPI/CIPO (Controller Out Peripheral In) nomenclature but that might become too verboragic. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + default: [0, 1, 2, 3, 4, 5, 6, 7] > + > spi-rx-delay-us: > description: > Delay, in microseconds, after a read transfer. > @@ -99,6 +106,13 @@ properties: > enum: [0, 1, 2, 4, 8] > default: [1] > > + spi-tx-lane-map: > + description: Mapping of peripheral TX lanes to controller TX lanes. > + Each index in the array represents a peripheral TX lane, and the value > + at that index represents the corresponding controller TX lane. Similar thoughts about the tx side.