[PATCH v10 0/4] PCI: imx6: Add external reference clock mode support

[PATCH v10 0/4] PCI: imx6: Add external reference clock mode support

[Richard Zhu]

I'm really sorry to send this version patch-set late, because that I was
engaged in other emergent tasks in the past weeks. And didn't have time
to continue this topic. Now, I have chance to continue doing this again.
Sorry to bring the inconvenience to the patch review.

i.MX95 PCIes have two reference clock inputs: one from internal PLL.
It's wired inside chip and present as "ref" clock. It's not an optional
clock. The other from off chip crystal oscillator. The "extref" clock
refers to a reference clock from an external crystal oscillator through
the CLKIN_N/P pair PADs. It is an optional clock, relied on the board
design.

Add additional optional external reference clock input for i.MX95 PCIes.

Main change in v10:
Thanks for Krzysztof's kindly review. 
- Change the miniItem of i.MX95 PCIe clocks from '4' to '5', since the "ref"
  clock is not optional. Update the commit message to describe why an
  additional optinal external reference clock input is added for i.MX95 PCIe.
- Add a new patch to fix the dtbs_check error after changing the miniItem of
  i.MX95 PCIe clocks in timx95-tqma9596sa-mb-smarc-2.dts.

Main change in v9:
Thanks for Conor's kindly review.
- Enlarge the maxItem of clocks for i.MX95 PCIe.
https://lore.kernel.org/imx/20251031031907.1390870-1-hongxing.zhu@nxp.com/

Main change in v8:
- Rebase to v6.18-rc1.
- No need to initialize bool parameter to the deault value "false" refer
  to Mani' comments in v7
https://lore.kernel.org/imx/20251024024013.775836-1-hongxing.zhu@nxp.com/

Main change in v7:
- Refine the subjects and commit message refer to Bjorn's comments.
https://lore.kernel.org/imx/20250918032555.3987157-1-hongxing.zhu@nxp.com/

Main change in v6:
- Refer to Krzysztof's comments, let i.MX95 PCIes has the "ref" clock
  since it is wired actually, and add one more optional "extref" clock
  for i.MX95 PCIes.
https://lore.kernel.org/imx/20250917045238.1048484-1-hongxing.zhu@nxp.com/

Main change in v5:
- Update the commit message of first patch refer to Bjorn's comments.
- Correct the typo error and update the description of property in the
  first patch.
https://lore.kernel.org/imx/20250915035348.3252353-1-hongxing.zhu@nxp.com/

Main change in v4:
- Add one more reference clock "extref" to be onhalf the reference clock
  that comes from external crystal oscillator.
https://lore.kernel.org/imx/20250626073804.3113757-1-hongxing.zhu@nxp.com/

Main change in v3:
- Update the logic check external reference clock mode is enabled or
  not in the driver codes.
https://lore.kernel.org/imx/20250620031350.674442-1-hongxing.zhu@nxp.com/

Main change in v2:
- Fix yamllint warning.
- Refine the driver codes.
https://lore.kernel.org/imx/20250619091004.338419-1-hongxing.zhu@nxp.com/

[PATCH v10 1/4] dt-bindings: PCI: dwc: Add external reference clock
[PATCH v10 2/4] dt-bindings: PCI: pci-imx6: Add external reference
[PATCH v10 3/4] PCI: imx6: Add external reference clock input mode
[PATCH v10 4/4] arm64: dt: imx95: Add the missed ref clock for

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml      |  7 +++++--
Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml |  6 ++++++
arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts  | 10 ++++++----
drivers/pci/controller/dwc/pci-imx6.c                          | 19 ++++++++++++-------
4 files changed, 29 insertions(+), 13 deletions(-)

[PATCH v10 1/4] dt-bindings: PCI: dwc: Add external reference clock input

[Richard Zhu]

Add external reference clock input "extref" for a reference clock that
comes from external crystal oscillator.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/pci/snps,dw-pcie-common.yaml        | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
index 34594972d8dbe..0134a759185ec 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
@@ -105,6 +105,12 @@ properties:
             define it with this name (for instance pipe, core and aux can
             be connected to a single source of the periodic signal).
           const: ref
+        - description:
+            Some dwc wrappers (like i.MX95 PCIes) have two reference clock
+            inputs, one from an internal PLL, the other from an off-chip crystal
+            oscillator. If present, 'extref' refers to a reference clock from
+            an external oscillator.
+          const: extref
         - description:
             Clock for the PHY registers interface. Originally this is
             a PHY-viewport-based interface, but some platform may have
-- 
2.37.1

[PATCH v10 2/4] dt-bindings: PCI: pci-imx6: Add external reference clock input

[Richard Zhu]

i.MX95 PCIes have two reference clock inputs: one from internal PLL.
It's wired inside chip and present as "ref" clock. It's not an optional
clock. The other from off chip crystal oscillator. The "extref" clock
refers to a reference clock from an external crystal oscillator through
the CLKIN_N/P pair PADs. It is an optional clock, relied on the board
design.

Add additional optional external reference clock input for i.MX95 PCIes.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index ca5f2970f217c..12a01f7a57443 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -44,7 +44,7 @@ properties:
 
   clock-names:
     minItems: 3
-    maxItems: 5
+    maxItems: 6
 
   interrupts:
     minItems: 1
@@ -212,14 +212,17 @@ allOf:
     then:
       properties:
         clocks:
-          maxItems: 5
+          minItems: 5
+          maxItems: 6
         clock-names:
+          minItems: 5
           items:
             - const: pcie
             - const: pcie_bus
             - const: pcie_phy
             - const: pcie_aux
             - const: ref
+            - const: extref  # Optional
 
 unevaluatedProperties: false
 
-- 
2.37.1

[PATCH v10 3/4] PCI: imx6: Add external reference clock input mode support

[Richard Zhu]

i.MX95 PCIes have two reference clock inputs: one from internal PLL, the
other from off chip crystal oscillator. The "extref" clock refers to a
reference clock from an external crystal oscillator.

Add external reference clock input mode support for i.MX95 PCIes.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 4668fc9648bff..a6db1f0f73c36 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -149,6 +149,7 @@ struct imx_pcie {
 	struct gpio_desc	*reset_gpiod;
 	struct clk_bulk_data	*clks;
 	int			num_clks;
+	bool			enable_ext_refclk;
 	struct regmap		*iomuxc_gpr;
 	u16			msi_ctrl;
 	u32			controller_id;
@@ -241,6 +242,8 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
 
 static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 {
+	bool ext = imx_pcie->enable_ext_refclk;
+
 	/*
 	 * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
 	 * Through Beacon or PERST# De-assertion
@@ -259,13 +262,12 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 			IMX95_PCIE_PHY_CR_PARA_SEL,
 			IMX95_PCIE_PHY_CR_PARA_SEL);
 
-	regmap_update_bits(imx_pcie->iomuxc_gpr,
-			   IMX95_PCIE_PHY_GEN_CTRL,
-			   IMX95_PCIE_REF_USE_PAD, 0);
-	regmap_update_bits(imx_pcie->iomuxc_gpr,
-			   IMX95_PCIE_SS_RW_REG_0,
+	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
+			   ext ? IMX95_PCIE_REF_USE_PAD : 0,
+			   IMX95_PCIE_REF_USE_PAD);
+	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
 			   IMX95_PCIE_REF_CLKEN,
-			   IMX95_PCIE_REF_CLKEN);
+			   ext ? 0 : IMX95_PCIE_REF_CLKEN);
 
 	return 0;
 }
@@ -1602,7 +1604,7 @@ static int imx_pcie_probe(struct platform_device *pdev)
 	struct imx_pcie *imx_pcie;
 	struct device_node *np;
 	struct device_node *node = dev->of_node;
-	int ret, domain;
+	int i, ret, domain;
 	u16 val;
 
 	imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
@@ -1653,6 +1655,9 @@ static int imx_pcie_probe(struct platform_device *pdev)
 	if (imx_pcie->num_clks < 0)
 		return dev_err_probe(dev, imx_pcie->num_clks,
 				     "failed to get clocks\n");
+	for (i = 0; i < imx_pcie->num_clks; i++)
+		if (strncmp(imx_pcie->clks[i].id, "extref", 6) == 0)
+			imx_pcie->enable_ext_refclk = true;
 
 	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
 		imx_pcie->phy = devm_phy_get(dev, "pcie-phy");
-- 
2.37.1

[PATCH v10 4/4] arm64: dt: imx95: Add the missed ref clock for PCIe[0,1]

[Richard Zhu]

i.MX95 PCIes have two reference clock inputs, one of them is from
internal PLL. It's wired inside chip and present as "ref" clock. It's
not an optional clock.

Add the missed ref clock for PCIe[0,1].

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 .../boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
index 5b6b2bb80b288..1258fcb54681e 100644
--- a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
@@ -237,8 +237,9 @@ &pcie0 {
 	clocks = <&scmi_clk IMX95_CLK_HSIO>,
 		 <&pcieclk 1>,
 		 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
-		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
-	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
+		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
+		 <&hsio_blk_ctl 0>;
+	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
 	reset-gpio = <&expander2 9 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
@@ -250,8 +251,9 @@ &pcie1 {
 	clocks = <&scmi_clk IMX95_CLK_HSIO>,
 		 <&pcieclk 0>,
 		 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
-		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
-	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
+		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
+		 <&hsio_blk_ctl 0>;
+	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
 	reset-gpio = <&expander2 10 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
-- 
2.37.1

Re: [PATCH v10 2/4] dt-bindings: PCI: pci-imx6: Add external reference clock input

[Rob Herring (Arm)]

On Thu, 11 Dec 2025 14:48:19 +0800, Richard Zhu wrote:
> i.MX95 PCIes have two reference clock inputs: one from internal PLL.
> It's wired inside chip and present as "ref" clock. It's not an optional
> clock. The other from off chip crystal oscillator. The "extref" clock
> refers to a reference clock from an external crystal oscillator through
> the CLKIN_N/P pair PADs. It is an optional clock, relied on the board
> design.
> 
> Add additional optional external reference clock input for i.MX95 PCIes.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: (subset) [PATCH v10 0/4] PCI: imx6: Add external reference clock mode support

[Manivannan Sadhasivam]

On Thu, 11 Dec 2025 14:48:17 +0800, Richard Zhu wrote:
> I'm really sorry to send this version patch-set late, because that I was
> engaged in other emergent tasks in the past weeks. And didn't have time
> to continue this topic. Now, I have chance to continue doing this again.
> Sorry to bring the inconvenience to the patch review.
> 
> i.MX95 PCIes have two reference clock inputs: one from internal PLL.
> It's wired inside chip and present as "ref" clock. It's not an optional
> clock. The other from off chip crystal oscillator. The "extref" clock
> refers to a reference clock from an external crystal oscillator through
> the CLKIN_N/P pair PADs. It is an optional clock, relied on the board
> design.
> 
> [...]

Applied, thanks!

[1/4] dt-bindings: PCI: dwc: Add external reference clock input
      commit: 418970983059aa06302ddd5ca76d441973b537c1
[2/4] dt-bindings: PCI: pci-imx6: Add external reference clock input
      commit: 1352f58d7c8dfb6ba0fbd2041bfc8b4b3966ec67
[3/4] PCI: imx6: Add external reference clock input mode support
      commit: d8574ce57d760a958623c8f6bc3c55b5187a7bd7

Best regards,
-- 
Manivannan Sadhasivam <mani@kernel.org>

Re: [PATCH v10 4/4] arm64: dt: imx95: Add the missed ref clock for PCIe[0,1]

[Shawn Guo]

On Thu, Dec 11, 2025 at 02:48:21PM +0800, Richard Zhu wrote:
> i.MX95 PCIes have two reference clock inputs, one of them is from
> internal PLL. It's wired inside chip and present as "ref" clock. It's
> not an optional clock.
> 
> Add the missed ref clock for PCIe[0,1].
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

It doesn't seem to apply to my tree.

Shawn

> ---
>  .../boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> index 5b6b2bb80b288..1258fcb54681e 100644
> --- a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> @@ -237,8 +237,9 @@ &pcie0 {
>  	clocks = <&scmi_clk IMX95_CLK_HSIO>,
>  		 <&pcieclk 1>,
>  		 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> -		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> -	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> +		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> +		 <&hsio_blk_ctl 0>;
> +	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
>  	reset-gpio = <&expander2 9 GPIO_ACTIVE_LOW>;
>  	status = "okay";
>  };
> @@ -250,8 +251,9 @@ &pcie1 {
>  	clocks = <&scmi_clk IMX95_CLK_HSIO>,
>  		 <&pcieclk 0>,
>  		 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> -		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> -	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> +		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> +		 <&hsio_blk_ctl 0>;
> +	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
>  	reset-gpio = <&expander2 10 GPIO_ACTIVE_LOW>;
>  	status = "okay";
>  };
> -- 
> 2.37.1
> 

RE: [PATCH v10 4/4] arm64: dt: imx95: Add the missed ref clock for PCIe[0,1]

[Hongxing Zhu]

> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: 2025年12月30日 11:28
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> bhelgaas@google.com; Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; imx@lists.linux.dev;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v10 4/4] arm64: dt: imx95: Add the missed ref clock for
> PCIe[0,1]
> 
> On Thu, Dec 11, 2025 at 02:48:21PM +0800, Richard Zhu wrote:
> > i.MX95 PCIes have two reference clock inputs, one of them is from
> > internal PLL. It's wired inside chip and present as "ref" clock. It's
> > not an optional clock.
> >
> > Add the missed ref clock for PCIe[0,1].
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> 
> It doesn't seem to apply to my tree.
Hi Shawn
Thanks for your concerns.
You're right.
I create this patch based on r6.18-rc1. And it wouldn’t be applied to r6.19-rc1.
Please ignore it. Thanks.

Best Regards
Richard Zhu
> 
> Shawn
> 
> > ---
> >  .../boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts | 10
> > ++++++----
> >  1 file changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git
> > a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> > b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> > index 5b6b2bb80b288..1258fcb54681e 100644
> > --- a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts
> > @@ -237,8 +237,9 @@ &pcie0 {
> >  	clocks = <&scmi_clk IMX95_CLK_HSIO>,
> >  		 <&pcieclk 1>,
> >  		 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> > -		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> > -	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> > +		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> > +		 <&hsio_blk_ctl 0>;
> > +	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
> >  	reset-gpio = <&expander2 9 GPIO_ACTIVE_LOW>;
> >  	status = "okay";
> >  };
> > @@ -250,8 +251,9 @@ &pcie1 {
> >  	clocks = <&scmi_clk IMX95_CLK_HSIO>,
> >  		 <&pcieclk 0>,
> >  		 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> > -		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> > -	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> > +		 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> > +		 <&hsio_blk_ctl 0>;
> > +	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
> >  	reset-gpio = <&expander2 10 GPIO_ACTIVE_LOW>;
> >  	status = "okay";
> >  };
> > --
> > 2.37.1
> >