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b=oY3ZQkiBNW6lgBspY/QM72BsYg eCV8rd9gLD4Wk3GCYQz2DQLCPcLmXEFq6ndzIluocwLsEl2gYCqjuYAWaegvIjTO/vSTrLctGAWNG HQnt5d8N5eoKnbjuGWjMIEuEuwdSUF3zxRSxF2RNTmdaqnX+gu0HWHGUUzNAVjRGfOXM=; Received: from [95.248.141.113] (port=63913 helo=bywater) by esm19.siteground.biz with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.1) (envelope-from ) id 1vadsD-000000007p2-0fef; Tue, 30 Dec 2025 17:51:09 +0000 Date: Tue, 30 Dec 2025 18:51:07 +0100 From: Francesco Valla To: Thomas Petazzoni Cc: Fabian Pflug , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Haidong Zheng , Danwei Luo , Lei Xu Subject: Re: [PATCH v4 2/2] arm64: dts: freescale: add support for NXP i.MX93 FRDM Message-ID: References: <20251218-fpg-nxp-imx93-frdm-v4-0-cd3a9f6ac89a@pengutronix.de> <20251218-fpg-nxp-imx93-frdm-v4-2-cd3a9f6ac89a@pengutronix.de> <20251230171548.67289601@windsurf> <20251230172427.4f22ac7c@windsurf> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251230172427.4f22ac7c@windsurf> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - esm19.siteground.biz X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - valla.it X-Source: X-Source-Args: X-Source-Dir: X-SGantispam-id: 8b55a54d1503179c2bfdf1e40b001bcf AntiSpam-DLS: false AntiSpam-DLSP: AntiSpam-DLSRS: AntiSpam-TS: 1.0 CFBL-Address: feedback@antispam.mailspamprotection.com; report=arf CFBL-Feedback-ID: 1vadsS-00000001IkR-340i-feedback@antispam.mailspamprotection.com Authentication-Results: outgoing.instance-europe-west4-7g44.prod.antispam.mailspamprotection.com; iprev=pass (214.173.214.35.bc.googleusercontent.com) smtp.remote-ip=35.214.173.214; auth=pass (LOGIN) smtp.auth=esm19.siteground.biz; dkim=pass header.d=valla.it header.s=default header.a=rsa-sha256; arc=none Hello Thomas, On Tue, Dec 30, 2025 at 05:24:27PM +0100, Thomas Petazzoni wrote: > Hello (again), > > On Tue, 30 Dec 2025 17:15:48 +0100 > Thomas Petazzoni wrote: > > > I see the PMIC interrupt and the RTC interrupts are routed to the I2C > > GPIO expander at 1-0022, so I imagine either the PMIC or the RTC are > > triggering an interrupt (left enabled by U-Boot), and the kernel isn't > > compiled with the driver for either the PMIC or the RTC, and therefore > > there's no IRQ handler? > > > > (I confess I didn't investigate more than that at this point.) > > Upon closer inspection, I in fact get thousands over IRQ #100 per > seconds right after boot, until the point where it reaches 100000 IRQ > events, and the splat appears, with the IRQ being subsequently > disabled. So it's not just one interrupt, but a storm of it. > This recalls the behaviour seen on i.MX91 FRDM [0], and the hardware is indeed very similar: the GPIO expander and the TypeC port controller (PTN5110) share the same IRQ line, and if the first gets enabled before the second an interrupt storm will happen (because the PTN5110 is triggering interrupts that nobody services). I did not see this during my testing - but maybe the probe sequence is different. Any chance you are not loading the driver for the PTN5110? I see from your defconfig it should be compiled as module, but maybe you are not including it into the image or not loading it? The NXP downstream BSP is masking interrupts for the TypeC port controller as part of the U-Boot initialization, as they are enabled by default at reset. While it somewhat breaks the required isolation between the bootloader and the system it loads, I fear this is the only sensible option here, given this hardware limitation; this was the path that was chosen for the i.MX91 FRDM (which has been applied today [1]). > Thomas > -- > Thomas Petazzoni, co-owner and CEO, Bootlin > Embedded Linux and Kernel engineering and training > https://bootlin.com > [0] https://lore.kernel.org/all/aTBFCc-8NzeS4MzT@bywater/ [1] https://lore.kernel.org/u-boot/CAOMZO5DsCi6GHrkvLEZTjsLy1D02A2e83YgMO36b3EMt8B6c5Q@mail.gmail.com/ Reagrds, Francesco