Re: [PATCH v5 3/9] spi: support controllers with multiple data lanes

[Andy Shevchenko <andriy.shevchenko@intel.com>]

On Fri, Jan 16, 2026 at 05:12:09PM -0600, David Lechner wrote:
> On 1/12/26 1:35 PM, Andy Shevchenko wrote:
> > On Mon, Jan 12, 2026 at 07:11:26PM +0000, Mark Brown wrote:
> >> On Mon, Jan 12, 2026 at 09:07:17PM +0200, Andy Shevchenko wrote:
> >>> On Mon, Jan 12, 2026 at 11:45:21AM -0600, David Lechner wrote:

...

> >>>> +	/* Multi-lane SPI controller support. */
> >>>> +	u32			tx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX];
> >>>> +	u32			num_tx_lanes;
> >>>> +	u32			rx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX];
> >>>> +	u32			num_rx_lanes;
> >>
> >>> This adds 72 bytes in _each_ instance of spi_device on the platforms that do
> >>> not use the feature and might not ever use it. Can we move to the pointer
> >>> and allocate the mentioned fields separately, please?
> >>
> >> Do we have real systems where we have enough SPI devices for anyone to
> >> care?
> > 
> > Define "enough" :-) To me even dozen of devices is enough (it gets almost a 1kB
> > of space) esp. if we are talking about quite low profile embedded systems.
> 
> We could make it u8 and save the same amount (on 64-bit systems) while avoiding
> the extra complexity of separate allocation.

Have you run `pahole` on this, btw? How big is it right now and do you fit
(aligned) with cache lines with this fields?

> I'm not particularly keen on requiring `/bits/ 8` in the devicetree though since
> it is unusual and often trips people up.

It can be transformed (to a smaller one) after reading
to a local (bigger) array.

-- 
With Best Regards,
Andy Shevchenko