From: Inochi Amaoto <inochiama@gmail.com>
To: Guodong Xu <guodong@riscstar.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Yixun Lan <dlan@gentoo.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Samuel Holland <samuel.holland@sifive.com>,
Anup Patel <anup@brainfault.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
Lubomir Rintel <lkundrak@v3.sk>, Yangyu Chen <cyy@cyyself.name>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Conor Dooley <conor@kernel.org>,
Heinrich Schuchardt <xypron.glpk@gmx.de>,
Kevin Meng Zhang <zhangmeng.kevin@linux.spacemit.com>,
Andrew Jones <ajones@ventanamicro.com>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, spacemit@lists.linux.dev,
linux-serial@vger.kernel.org
Subject: Re: [PATCH v4 10/11] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC
Date: Sat, 10 Jan 2026 18:00:00 +0800 [thread overview]
Message-ID: <aWIi9LFdqSF3c-FP@inochi.infowork> (raw)
In-Reply-To: <20260110-k3-basic-dt-v4-10-d492f3a30ffa@riscstar.com>
On Sat, Jan 10, 2026 at 01:18:22PM +0800, Guodong Xu wrote:
> SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant.
> Add nodes of uarts, timer and interrupt-controllers.
>
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
> v4: Fix missing blank space after commas in compatible string.
> Add m-mode imsic and aplic node.
> Reorder properties in simsic, saplic, mimsic, and maplic nodes
> to match DTS coding style.
> v3: Remove "supm" from the riscv,isa-extensions list.
> v2: Remove aliases from k3.dtsi, they should be in board DTS.
> Updated riscv,isa-extensions with new extensions from the extensions.yaml.
> ---
> arch/riscv/boot/dts/spacemit/k3.dtsi | 590 +++++++++++++++++++++++++++++++++++
> 1 file changed, 590 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> new file mode 100644
> index 000000000000..a815f85cf5a6
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -0,0 +1,590 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2025 SpacemiT (Hangzhou) Technology Co. Ltd
> + * Copyright (c) 2025 Guodong Xu <guodong@riscstar.com>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/dts-v1/;
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "SpacemiT K3";
> + compatible = "spacemit,k3";
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <24000000>;
> +
> + cpu_0: cpu@0 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> + "sha", "shcounterenw", "shgatpa", "shtvala",
> + "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> + "smstateen", "ssaia", "ssccptr", "sscofpmf",
> + "sscounterenw", "ssnpm", "ssstateen", "sstc",
> + "sstvala", "sstvecd", "ssu64xl", "svade",
> + "svinval", "svnapot", "svpbmt", "za64rs",
> + "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> + "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "ziccamoa", "ziccif", "zicclsm", "zicntr",
> + "zicond", "zicsr", "zifencei", "zihintntl",
> + "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache0>;
> + mmu-type = "riscv,sv39";
I think this should be riscv,sv48? IIRC K3 supports it.
Regards,
Inochi
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_1: cpu@1 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <1>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> + "sha", "shcounterenw", "shgatpa", "shtvala",
> + "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> + "smstateen", "ssaia", "ssccptr", "sscofpmf",
> + "sscounterenw", "ssnpm", "ssstateen", "sstc",
> + "sstvala", "sstvecd", "ssu64xl", "svade",
> + "svinval", "svnapot", "svpbmt", "za64rs",
> + "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> + "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "ziccamoa", "ziccif", "zicclsm", "zicntr",
> + "zicond", "zicsr", "zifencei", "zihintntl",
> + "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache0>;
> + mmu-type = "riscv,sv39";
> +
> + cpu1_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_2: cpu@2 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <2>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> + "sha", "shcounterenw", "shgatpa", "shtvala",
> + "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> + "smstateen", "ssaia", "ssccptr", "sscofpmf",
> + "sscounterenw", "ssnpm", "ssstateen", "sstc",
> + "sstvala", "sstvecd", "ssu64xl", "svade",
> + "svinval", "svnapot", "svpbmt", "za64rs",
> + "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> + "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "ziccamoa", "ziccif", "zicclsm", "zicntr",
> + "zicond", "zicsr", "zifencei", "zihintntl",
> + "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache0>;
> + mmu-type = "riscv,sv39";
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_3: cpu@3 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <3>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> + "sha", "shcounterenw", "shgatpa", "shtvala",
> + "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> + "smstateen", "ssaia", "ssccptr", "sscofpmf",
> + "sscounterenw", "ssnpm", "ssstateen", "sstc",
> + "sstvala", "sstvecd", "ssu64xl", "svade",
> + "svinval", "svnapot", "svpbmt", "za64rs",
> + "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> + "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "ziccamoa", "ziccif", "zicclsm", "zicntr",
> + "zicond", "zicsr", "zifencei", "zihintntl",
> + "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache0>;
> + mmu-type = "riscv,sv39";
> +
> + cpu3_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_4: cpu@4 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <4>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> + "sha", "shcounterenw", "shgatpa", "shtvala",
> + "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> + "smstateen", "ssaia", "ssccptr", "sscofpmf",
> + "sscounterenw", "ssnpm", "ssstateen", "sstc",
> + "sstvala", "sstvecd", "ssu64xl", "svade",
> + "svinval", "svnapot", "svpbmt", "za64rs",
> + "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> + "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "ziccamoa", "ziccif", "zicclsm", "zicntr",
> + "zicond", "zicsr", "zifencei", "zihintntl",
> + "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache1>;
> + mmu-type = "riscv,sv39";
> +
> + cpu4_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_5: cpu@5 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <5>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> + "sha", "shcounterenw", "shgatpa", "shtvala",
> + "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> + "smstateen", "ssaia", "ssccptr", "sscofpmf",
> + "sscounterenw", "ssnpm", "ssstateen", "sstc",
> + "sstvala", "sstvecd", "ssu64xl", "svade",
> + "svinval", "svnapot", "svpbmt", "za64rs",
> + "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> + "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "ziccamoa", "ziccif", "zicclsm", "zicntr",
> + "zicond", "zicsr", "zifencei", "zihintntl",
> + "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache1>;
> + mmu-type = "riscv,sv39";
> +
> + cpu5_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_6: cpu@6 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <6>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> + "sha", "shcounterenw", "shgatpa", "shtvala",
> + "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> + "smstateen", "ssaia", "ssccptr", "sscofpmf",
> + "sscounterenw", "ssnpm", "ssstateen", "sstc",
> + "sstvala", "sstvecd", "ssu64xl", "svade",
> + "svinval", "svnapot", "svpbmt", "za64rs",
> + "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> + "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "ziccamoa", "ziccif", "zicclsm", "zicntr",
> + "zicond", "zicsr", "zifencei", "zihintntl",
> + "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache1>;
> + mmu-type = "riscv,sv39";
> +
> + cpu6_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_7: cpu@7 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <7>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
> + "sha", "shcounterenw", "shgatpa", "shtvala",
> + "shvsatpa", "shvstvala", "shvstvecd", "smaia",
> + "smstateen", "ssaia", "ssccptr", "sscofpmf",
> + "sscounterenw", "ssnpm", "ssstateen", "sstc",
> + "sstvala", "sstvecd", "ssu64xl", "svade",
> + "svinval", "svnapot", "svpbmt", "za64rs",
> + "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
> + "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "ziccamoa", "ziccif", "zicclsm", "zicntr",
> + "zicond", "zicsr", "zifencei", "zihintntl",
> + "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
> + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
> + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
> + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
> + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache1>;
> + mmu-type = "riscv,sv39";
> +
> + cpu7_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + l2_cache0: cache-controller-0 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-size = <4194304>;
> + cache-sets = <4096>;
> + cache-unified;
> + };
> +
> + l2_cache1: cache-controller-1 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-size = <4194304>;
> + cache-sets = <4096>;
> + cache-unified;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu_0>;
> + };
> + core1 {
> + cpu = <&cpu_1>;
> + };
> + core2 {
> + cpu = <&cpu_2>;
> + };
> + core3 {
> + cpu = <&cpu_3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu_4>;
> + };
> + core1 {
> + cpu = <&cpu_5>;
> + };
> + core2 {
> + cpu = <&cpu_6>;
> + };
> + core3 {
> + cpu = <&cpu_7>;
> + };
> + };
> + };
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&saplic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-noncoherent;
> + ranges;
> +
> + uart0: serial@d4017000 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017000 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
> +
> + status = "disabled";
> + };
> +
> + uart2: serial@d4017100 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017100 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> +
> + status = "disabled";
> + };
> +
> + uart3: serial@d4017200 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017200 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> +
> + status = "disabled";
> + };
> +
> + uart4: serial@d4017300 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017300 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> +
> + status = "disabled";
> + };
> +
> + uart5: serial@d4017400 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017400 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> +
> + status = "disabled";
> + };
> +
> + uart6: serial@d4017500 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017500 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> +
> + status = "disabled";
> + };
> +
> + uart7: serial@d4017600 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017600 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> +
> + status = "disabled";
> + };
> +
> + uart8: serial@d4017700 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017700 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> +
> + status = "disabled";
> + };
> +
> + uart9: serial@d4017800 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017800 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
> +
> + status = "disabled";
> + };
> +
> + uart10: serial@d401f000 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd401f000 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <281 IRQ_TYPE_LEVEL_HIGH>;
> +
> + status = "disabled";
> + };
> +
> + simsic: interrupt-controller@e0400000 {
> + compatible = "spacemit,k3-imsics", "riscv,imsics";
> + reg = <0x0 0xe0400000 0x0 0x200000>;
> + #interrupt-cells = <0>;
> + #msi-cells = <0>;
> + interrupt-controller;
> + interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
> + <&cpu2_intc 9>, <&cpu3_intc 9>,
> + <&cpu4_intc 9>, <&cpu5_intc 9>,
> + <&cpu6_intc 9>, <&cpu7_intc 9>;
> + msi-controller;
> + riscv,guest-index-bits = <6>;
> + riscv,hart-index-bits = <4>;
> + riscv,num-guest-ids = <511>;
> + riscv,num-ids = <511>;
> + };
> +
> + saplic: interrupt-controller@e0804000 {
> + compatible = "spacemit,k3-aplic", "riscv,aplic";
> + reg = <0x0 0xe0804000 0x0 0x4000>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + msi-parent = <&simsic>;
> + riscv,num-sources = <512>;
> + };
> +
> + clint: timer@e081c000 {
> + compatible = "spacemit,k3-clint", "sifive,clint0";
> + reg = <0x0 0xe081c000 0x0 0x4000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>,
> + <&cpu4_intc 3>, <&cpu4_intc 7>,
> + <&cpu5_intc 3>, <&cpu5_intc 7>,
> + <&cpu6_intc 3>, <&cpu6_intc 7>,
> + <&cpu7_intc 3>, <&cpu7_intc 7>;
> + };
> +
> + mimsic: interrupt-controller@f1000000 {
> + compatible = "spacemit,k3-imsics", "riscv,imsics";
> + reg = <0x0 0xf1000000 0x0 0x10000>;
> + #interrupt-cells = <0>;
> + #msi-cells = <0>;
> + interrupt-controller;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
> + <&cpu2_intc 11>, <&cpu3_intc 11>,
> + <&cpu4_intc 11>, <&cpu5_intc 11>,
> + <&cpu6_intc 11>, <&cpu7_intc 11>;
> + msi-controller;
> + riscv,guest-index-bits = <6>;
> + riscv,hart-index-bits = <4>;
> + riscv,num-guest-ids = <511>;
> + riscv,num-ids = <511>;
> +
> + status = "disabled";
> + };
> +
> + maplic: interrupt-controller@f1800000 {
> + compatible = "spacemit,k3-aplic", "riscv,aplic";
> + reg = <0x0 0xf1800000 0x0 0x4000>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + msi-parent = <&mimsic>;
> + riscv,children = <&saplic>;
> + riscv,delegate = <&saplic 1 512>;
> + riscv,num-sources = <512>;
> +
> + status = "disabled";
> + };
> + };
> +};
>
> --
> 2.43.0
>
>
next prev parent reply other threads:[~2026-01-10 10:00 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-10 5:18 [PATCH v4 00/11] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board Guodong Xu
2026-01-10 5:18 ` [PATCH v4 01/11] dt-bindings: riscv: add SpacemiT X100 CPU compatible Guodong Xu
2026-01-14 23:27 ` Paul Walmsley
2026-01-10 5:18 ` [PATCH v4 02/11] dt-bindings: timer: add SpacemiT K3 CLINT Guodong Xu
2026-01-10 5:18 ` [PATCH v4 03/11] dt-bindings: interrupt-controller: add SpacemiT K3 APLIC Guodong Xu
2026-01-10 5:18 ` [PATCH v4 04/11] dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC Guodong Xu
2026-01-10 5:18 ` [PATCH v4 05/11] dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings Guodong Xu
2026-01-10 11:55 ` Yixun Lan
2026-01-12 21:37 ` Conor Dooley
2026-01-10 5:18 ` [PATCH v4 06/11] dt-bindings: riscv: Add B ISA extension description Guodong Xu
2026-01-12 21:41 ` Conor Dooley
2026-01-13 2:44 ` Guodong Xu
2026-01-10 5:18 ` [PATCH v4 07/11] dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm Guodong Xu
2026-01-12 21:38 ` Conor Dooley
2026-01-10 5:18 ` [PATCH v4 08/11] dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl Guodong Xu
2026-01-12 21:39 ` Conor Dooley
2026-01-10 5:18 ` [PATCH v4 09/11] dt-bindings: riscv: Add Sha and its comprised extensions Guodong Xu
2026-01-12 21:40 ` Conor Dooley
2026-01-10 5:18 ` [PATCH v4 10/11] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC Guodong Xu
2026-01-10 10:00 ` Inochi Amaoto [this message]
2026-01-10 11:05 ` Yixun Lan
2026-01-12 8:14 ` Guodong Xu
2026-01-12 7:42 ` Maud Spierings
2026-01-12 7:59 ` Guodong Xu
2026-01-10 5:18 ` [PATCH v4 11/11] riscv: dts: spacemit: add SpacemiT K3 Pico-ITX board device tree Guodong Xu
2026-01-10 9:57 ` Yixun Lan
2026-01-12 8:57 ` Guodong Xu
2026-01-12 21:45 ` [PATCH v4 00/11] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board Conor Dooley
2026-01-13 0:21 ` Yixun Lan
2026-01-13 22:17 ` Conor Dooley
2026-01-14 2:14 ` Yixun Lan
2026-01-14 20:26 ` Rob Herring
2026-01-13 2:51 ` Guodong Xu
2026-01-13 22:25 ` (subset) " Conor Dooley
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