[PATCH 0/5] Add DisplayPort support for rk3576

[PATCH 0/5] Add DisplayPort support for rk3576

[Andy Yan]

From: Andy Yan <andy.yan@rock-chips.com>


The DisplayPort found on RK3576 is very similar to that of RK3588,
but work in qual pixel mode and support for MST.

This patch series aims to add basic display output, not include audio
and MST, which will be the work for the next stage.

Only test with 2 lane standard DP port output now.



Andy Yan (5):
  dt-bindings: display: rockchip: Add rk3576 DisplayPort
  drm/bridge: synopsys: dw-dp: Set pixel mode by platform data
  drm/bridge: synopsys: dw-dp: Make i2s/spdif clk optional
  drm/rockchip: dw_dp: Add DisplayPort support for rk3576
  arm64: dts: rockchip: Add DisplayPort dt node for rk3576

 .../display/rockchip/rockchip,dw-dp.yaml      | 29 +++++++++++++++++--
 arch/arm64/boot/dts/rockchip/rk3576.dtsi      | 28 ++++++++++++++++++
 drivers/gpu/drm/bridge/synopsys/dw-dp.c       | 12 ++------
 drivers/gpu/drm/rockchip/dw_dp-rockchip.c     | 27 ++++++++++++++---
 include/drm/bridge/dw_dp.h                    |  7 +++++
 5 files changed, 87 insertions(+), 16 deletions(-)

-- 
2.43.0

base-commit: ad939ed1f8108513e84e93da90ad7ea31b56ef87
branch: rk3576-dp-upstream

[PATCH 1/5] dt-bindings: display: rockchip: Add rk3576 DisplayPort

[Andy Yan]

From: Andy Yan <andy.yan@rock-chips.com>

The DisplayPort found on RK3576 is very similar to that of RK3588,
but work in dual pixel mode. And itself does not depend on the I2S
clock or the SPDIF clock when transmit audio.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

---

 .../display/rockchip/rockchip,dw-dp.yaml      | 29 +++++++++++++++++--
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
index 6345f0132d43..1bfe1bd6404a 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
@@ -27,13 +27,11 @@ description: |
   * Pixel clock up to 594MHz
   * I2S, SPDIF audio interface
 
-allOf:
-  - $ref: /schemas/sound/dai-common.yaml#
-
 properties:
   compatible:
     enum:
       - rockchip,rk3588-dp
+      - rockchip,rk3576-dp
 
   reg:
     maxItems: 1
@@ -42,6 +40,7 @@ properties:
     maxItems: 1
 
   clocks:
+    minItems: 3
     items:
       - description: Peripheral/APB bus clock
       - description: DisplayPort AUX clock
@@ -50,6 +49,7 @@ properties:
       - description: SPDIF interfce clock
 
   clock-names:
+    minItems: 3
     items:
       - const: apb
       - const: aux
@@ -95,6 +95,29 @@ required:
   - ports
   - resets
 
+allOf:
+  - $ref: /schemas/sound/dai-common.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - rockchip,rk3588-dp
+    then:
+      properties:
+        clocks:
+          minItems: 5
+          maxItems: 5
+        clock-names:
+          minItems: 5
+          maxItems: 5
+    else:
+      properties:
+        clocks:
+          maxItems: 3
+        clock-names:
+          maxItems: 3
+
 unevaluatedProperties: false
 
 examples:
-- 
2.43.0

[PATCH 2/5] drm/bridge: synopsys: dw-dp: Set pixel mode by platform data

[Andy Yan]

From: Andy Yan <andy.yan@rock-chips.com>

The DW DisplayPort hardware block can be configured to work in single,
dual,quad pixel mode on differnt platforms, so make the pixel mode set
by plat_data to support the upcoming rk3576 variant.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---

 drivers/gpu/drm/bridge/synopsys/dw-dp.c   |  8 +-------
 drivers/gpu/drm/rockchip/dw_dp-rockchip.c | 19 +++++++++++++++----
 include/drm/bridge/dw_dp.h                |  7 +++++++
 3 files changed, 23 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-dp.c b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
index 82aaf74e1bc0..eccf6299bdb7 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-dp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
@@ -352,12 +352,6 @@ enum {
 	DW_DP_YCBCR420_16BIT,
 };
 
-enum {
-	DW_DP_MP_SINGLE_PIXEL,
-	DW_DP_MP_DUAL_PIXEL,
-	DW_DP_MP_QUAD_PIXEL,
-};
-
 enum {
 	DW_DP_SDP_VERTICAL_INTERVAL = BIT(0),
 	DW_DP_SDP_HORIZONTAL_INTERVAL = BIT(1),
@@ -1984,7 +1978,7 @@ struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
 		return ERR_CAST(dp);
 
 	dp->dev = dev;
-	dp->pixel_mode = DW_DP_MP_QUAD_PIXEL;
+	dp->pixel_mode = plat_data->pixel_mode;
 
 	dp->plat_data.max_link_rate = plat_data->max_link_rate;
 	bridge = &dp->bridge;
diff --git a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
index 25ab4e46301e..89d614d53596 100644
--- a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
@@ -75,7 +75,7 @@ static const struct drm_encoder_helper_funcs dw_dp_encoder_helper_funcs = {
 static int dw_dp_rockchip_bind(struct device *dev, struct device *master, void *data)
 {
 	struct platform_device *pdev = to_platform_device(dev);
-	struct dw_dp_plat_data plat_data;
+	const struct dw_dp_plat_data *plat_data;
 	struct drm_device *drm_dev = data;
 	struct rockchip_dw_dp *dp;
 	struct drm_encoder *encoder;
@@ -89,7 +89,10 @@ static int dw_dp_rockchip_bind(struct device *dev, struct device *master, void *
 	dp->dev = dev;
 	platform_set_drvdata(pdev, dp);
 
-	plat_data.max_link_rate = 810000;
+	plat_data = of_device_get_match_data(dev);
+	if (!plat_data)
+		return -ENODEV;
+
 	encoder = &dp->encoder.encoder;
 	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, dev->of_node);
 	rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder, dev->of_node, 0, 0);
@@ -99,7 +102,7 @@ static int dw_dp_rockchip_bind(struct device *dev, struct device *master, void *
 		return ret;
 	drm_encoder_helper_add(encoder, &dw_dp_encoder_helper_funcs);
 
-	dp->base = dw_dp_bind(dev, encoder, &plat_data);
+	dp->base = dw_dp_bind(dev, encoder, plat_data);
 	if (IS_ERR(dp->base)) {
 		ret = PTR_ERR(dp->base);
 		return ret;
@@ -134,8 +137,16 @@ static void dw_dp_remove(struct platform_device *pdev)
 	component_del(dp->dev, &dw_dp_rockchip_component_ops);
 }
 
+static const struct dw_dp_plat_data rk3588_dp_plat_data = {
+	.max_link_rate = 810000,
+	.pixel_mode = DW_DP_MP_QUAD_PIXEL,
+};
+
 static const struct of_device_id dw_dp_of_match[] = {
-	{ .compatible = "rockchip,rk3588-dp", },
+	{
+		.compatible = "rockchip,rk3588-dp",
+		.data = &rk3588_dp_plat_data,
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, dw_dp_of_match);
diff --git a/include/drm/bridge/dw_dp.h b/include/drm/bridge/dw_dp.h
index d05df49fd884..25363541e69d 100644
--- a/include/drm/bridge/dw_dp.h
+++ b/include/drm/bridge/dw_dp.h
@@ -11,8 +11,15 @@
 struct drm_encoder;
 struct dw_dp;
 
+enum {
+	DW_DP_MP_SINGLE_PIXEL,
+	DW_DP_MP_DUAL_PIXEL,
+	DW_DP_MP_QUAD_PIXEL,
+};
+
 struct dw_dp_plat_data {
 	u32 max_link_rate;
+	u8 pixel_mode;
 };
 
 struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
-- 
2.43.0

[PATCH 3/5] drm/bridge: synopsys: dw-dp: Make i2s/spdif clk optional

[Andy Yan]

From: Andy Yan <andy.yan@rock-chips.com>

The i2s/spdif clk are mandatory for rk3588, but not used
for the upcoming rk3576, so make it optional here.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---

 drivers/gpu/drm/bridge/synopsys/dw-dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-dp.c b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
index eccf6299bdb7..93e3efe18957 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-dp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
@@ -2014,13 +2014,13 @@ struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
 		return ERR_CAST(dp->aux_clk);
 	}
 
-	dp->i2s_clk = devm_clk_get(dev, "i2s");
+	dp->i2s_clk = devm_clk_get_optional(dev, "i2s");
 	if (IS_ERR(dp->i2s_clk)) {
 		dev_err_probe(dev, PTR_ERR(dp->i2s_clk), "failed to get i2s clock\n");
 		return ERR_CAST(dp->i2s_clk);
 	}
 
-	dp->spdif_clk = devm_clk_get(dev, "spdif");
+	dp->spdif_clk = devm_clk_get_optional(dev, "spdif");
 	if (IS_ERR(dp->spdif_clk)) {
 		dev_err_probe(dev, PTR_ERR(dp->spdif_clk), "failed to get spdif clock\n");
 		return ERR_CAST(dp->spdif_clk);
-- 
2.43.0

[PATCH 4/5] drm/rockchip: dw_dp: Add DisplayPort support for rk3576

[Andy Yan]

From: Andy Yan <andy.yan@rock-chips.com>

The DisplayPort of the RK3576 is basically the same as that of the
RK3588, but it operates in dual-pixel mode and also support MST.

This patch only enable the SST output now.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---

 drivers/gpu/drm/rockchip/dw_dp-rockchip.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
index 89d614d53596..dac3d202971e 100644
--- a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
@@ -142,10 +142,18 @@ static const struct dw_dp_plat_data rk3588_dp_plat_data = {
 	.pixel_mode = DW_DP_MP_QUAD_PIXEL,
 };
 
+static const struct dw_dp_plat_data rk3576_dp_plat_data = {
+	.max_link_rate = 810000,
+	.pixel_mode = DW_DP_MP_DUAL_PIXEL,
+};
+
 static const struct of_device_id dw_dp_of_match[] = {
 	{
 		.compatible = "rockchip,rk3588-dp",
 		.data = &rk3588_dp_plat_data,
+	}, {
+		.compatible = "rockchip,rk3576-dp",
+		.data = &rk3576_dp_plat_data,
 	},
 	{}
 };
-- 
2.43.0

[PATCH 5/5] arm64: dts: rockchip: Add DisplayPort dt node for rk3576

[Andy Yan]

From: Andy Yan <andy.yan@rock-chips.com>

The DisplayPort on rk3576 is compliant with DisplayPort Specification
Version 1.4 with MST support, and share the USBDP combo PHY with USB 3.1
OTG0 controller.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---

 arch/arm64/boot/dts/rockchip/rk3576.dtsi | 28 ++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index a86fc6b4e8c4..a153c3976cb3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1446,6 +1446,34 @@ hdmi_out: port@1 {
 			};
 		};
 
+		dp: dp@27e40000 {
+			compatible = "rockchip,rk3576-dp";
+			reg = <0x0 0x27e40000 0x0 0x30000>;
+			interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+			assigned-clocks = <&cru CLK_AUX16MHZ_0>;
+			assigned-clock-rates = <16000000>;
+			clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16MHZ_0>,
+				 <&cru ACLK_DP0>;
+			clock-names = "apb", "aux", "hdcp";
+			resets = <&cru SRST_DP0>;
+			phys = <&usbdp_phy PHY_TYPE_DP>;
+			power-domains = <&power RK3576_PD_VO1>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dp0_in: port@0 {
+					reg = <0>;
+				};
+
+				dp0_out: port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
 		sai7: sai@27ed0000 {
 			compatible = "rockchip,rk3576-sai";
 			reg = <0x0 0x27ed0000 0x0 0x1000>;
-- 
2.43.0

Re: [PATCH 1/5] dt-bindings: display: rockchip: Add rk3576 DisplayPort

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 2453 bytes --]

Hi,

On Fri, Jan 09, 2026 at 04:00:44PM +0800, Andy Yan wrote:
> From: Andy Yan <andy.yan@rock-chips.com>
> 
> The DisplayPort found on RK3576 is very similar to that of RK3588,
> but work in dual pixel mode. And itself does not depend on the I2S
> clock or the SPDIF clock when transmit audio.
> 
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> 
> ---
> 
>  .../display/rockchip/rockchip,dw-dp.yaml      | 29 +++++++++++++++++--
>  1 file changed, 26 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
> index 6345f0132d43..1bfe1bd6404a 100644
> --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
> @@ -27,13 +27,11 @@ description: |
>    * Pixel clock up to 594MHz
>    * I2S, SPDIF audio interface
>  
> -allOf:
> -  - $ref: /schemas/sound/dai-common.yaml#
> -
>  properties:
>    compatible:
>      enum:
>        - rockchip,rk3588-dp
> +      - rockchip,rk3576-dp
>  
>    reg:
>      maxItems: 1
> @@ -42,6 +40,7 @@ properties:
>      maxItems: 1
>  
>    clocks:
> +    minItems: 3
>      items:
>        - description: Peripheral/APB bus clock
>        - description: DisplayPort AUX clock
> @@ -50,6 +49,7 @@ properties:
>        - description: SPDIF interfce clock
>  
>    clock-names:
> +    minItems: 3
>      items:
>        - const: apb
>        - const: aux
> @@ -95,6 +95,29 @@ required:
>    - ports
>    - resets
>  
> +allOf:
> +  - $ref: /schemas/sound/dai-common.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - rockchip,rk3588-dp
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 5
> +          maxItems: 5
> +        clock-names:
> +          minItems: 5
> +          maxItems: 5

I think maxItems is not needed, since 6 items would not work for the
specified items list anyways. Otherwise:

Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>

Greetings,

-- Sebastian

> +    else:
> +      properties:
> +        clocks:
> +          maxItems: 3
> +        clock-names:
> +          maxItems: 3
> +
>  unevaluatedProperties: false
>  
>  examples:
> -- 
> 2.43.0
> 

[-- Attachment #2: signature.asc --]
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Re: [PATCH 2/5] drm/bridge: synopsys: dw-dp: Set pixel mode by platform data

[Sebastian Reichel]

Hi,

On Fri, Jan 09, 2026 at 04:00:45PM +0800, Andy Yan wrote:
> From: Andy Yan <andy.yan@rock-chips.com>
> 
> The DW DisplayPort hardware block can be configured to work in single,
> dual,quad pixel mode on differnt platforms, so make the pixel mode set
> by plat_data to support the upcoming rk3576 variant.
> 
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---

Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com>

Greetings,

-- Sebastian

> 
>  drivers/gpu/drm/bridge/synopsys/dw-dp.c   |  8 +-------
>  drivers/gpu/drm/rockchip/dw_dp-rockchip.c | 19 +++++++++++++++----
>  include/drm/bridge/dw_dp.h                |  7 +++++++
>  3 files changed, 23 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-dp.c b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
> index 82aaf74e1bc0..eccf6299bdb7 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-dp.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
> @@ -352,12 +352,6 @@ enum {
>  	DW_DP_YCBCR420_16BIT,
>  };
>  
> -enum {
> -	DW_DP_MP_SINGLE_PIXEL,
> -	DW_DP_MP_DUAL_PIXEL,
> -	DW_DP_MP_QUAD_PIXEL,
> -};
> -
>  enum {
>  	DW_DP_SDP_VERTICAL_INTERVAL = BIT(0),
>  	DW_DP_SDP_HORIZONTAL_INTERVAL = BIT(1),
> @@ -1984,7 +1978,7 @@ struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
>  		return ERR_CAST(dp);
>  
>  	dp->dev = dev;
> -	dp->pixel_mode = DW_DP_MP_QUAD_PIXEL;
> +	dp->pixel_mode = plat_data->pixel_mode;
>  
>  	dp->plat_data.max_link_rate = plat_data->max_link_rate;
>  	bridge = &dp->bridge;
> diff --git a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
> index 25ab4e46301e..89d614d53596 100644
> --- a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
> @@ -75,7 +75,7 @@ static const struct drm_encoder_helper_funcs dw_dp_encoder_helper_funcs = {
>  static int dw_dp_rockchip_bind(struct device *dev, struct device *master, void *data)
>  {
>  	struct platform_device *pdev = to_platform_device(dev);
> -	struct dw_dp_plat_data plat_data;
> +	const struct dw_dp_plat_data *plat_data;
>  	struct drm_device *drm_dev = data;
>  	struct rockchip_dw_dp *dp;
>  	struct drm_encoder *encoder;
> @@ -89,7 +89,10 @@ static int dw_dp_rockchip_bind(struct device *dev, struct device *master, void *
>  	dp->dev = dev;
>  	platform_set_drvdata(pdev, dp);
>  
> -	plat_data.max_link_rate = 810000;
> +	plat_data = of_device_get_match_data(dev);
> +	if (!plat_data)
> +		return -ENODEV;
> +
>  	encoder = &dp->encoder.encoder;
>  	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, dev->of_node);
>  	rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder, dev->of_node, 0, 0);
> @@ -99,7 +102,7 @@ static int dw_dp_rockchip_bind(struct device *dev, struct device *master, void *
>  		return ret;
>  	drm_encoder_helper_add(encoder, &dw_dp_encoder_helper_funcs);
>  
> -	dp->base = dw_dp_bind(dev, encoder, &plat_data);
> +	dp->base = dw_dp_bind(dev, encoder, plat_data);
>  	if (IS_ERR(dp->base)) {
>  		ret = PTR_ERR(dp->base);
>  		return ret;
> @@ -134,8 +137,16 @@ static void dw_dp_remove(struct platform_device *pdev)
>  	component_del(dp->dev, &dw_dp_rockchip_component_ops);
>  }
>  
> +static const struct dw_dp_plat_data rk3588_dp_plat_data = {
> +	.max_link_rate = 810000,
> +	.pixel_mode = DW_DP_MP_QUAD_PIXEL,
> +};
> +
>  static const struct of_device_id dw_dp_of_match[] = {
> -	{ .compatible = "rockchip,rk3588-dp", },
> +	{
> +		.compatible = "rockchip,rk3588-dp",
> +		.data = &rk3588_dp_plat_data,
> +	},
>  	{}
>  };
>  MODULE_DEVICE_TABLE(of, dw_dp_of_match);
> diff --git a/include/drm/bridge/dw_dp.h b/include/drm/bridge/dw_dp.h
> index d05df49fd884..25363541e69d 100644
> --- a/include/drm/bridge/dw_dp.h
> +++ b/include/drm/bridge/dw_dp.h
> @@ -11,8 +11,15 @@
>  struct drm_encoder;
>  struct dw_dp;
>  
> +enum {
> +	DW_DP_MP_SINGLE_PIXEL,
> +	DW_DP_MP_DUAL_PIXEL,
> +	DW_DP_MP_QUAD_PIXEL,
> +};
> +
>  struct dw_dp_plat_data {
>  	u32 max_link_rate;
> +	u8 pixel_mode;
>  };
>  
>  struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
> -- 
> 2.43.0
> 

Re: [PATCH 3/5] drm/bridge: synopsys: dw-dp: Make i2s/spdif clk optional

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 1490 bytes --]

Hi,

On Fri, Jan 09, 2026 at 04:00:46PM +0800, Andy Yan wrote:
> From: Andy Yan <andy.yan@rock-chips.com>
> 
> The i2s/spdif clk are mandatory for rk3588, but not used
> for the upcoming rk3576, so make it optional here.
> 
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---

Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com>

Greetings,

-- Sebastian

>  drivers/gpu/drm/bridge/synopsys/dw-dp.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-dp.c b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
> index eccf6299bdb7..93e3efe18957 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-dp.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
> @@ -2014,13 +2014,13 @@ struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
>  		return ERR_CAST(dp->aux_clk);
>  	}
>  
> -	dp->i2s_clk = devm_clk_get(dev, "i2s");
> +	dp->i2s_clk = devm_clk_get_optional(dev, "i2s");
>  	if (IS_ERR(dp->i2s_clk)) {
>  		dev_err_probe(dev, PTR_ERR(dp->i2s_clk), "failed to get i2s clock\n");
>  		return ERR_CAST(dp->i2s_clk);
>  	}
>  
> -	dp->spdif_clk = devm_clk_get(dev, "spdif");
> +	dp->spdif_clk = devm_clk_get_optional(dev, "spdif");
>  	if (IS_ERR(dp->spdif_clk)) {
>  		dev_err_probe(dev, PTR_ERR(dp->spdif_clk), "failed to get spdif clock\n");
>  		return ERR_CAST(dp->spdif_clk);
> -- 
> 2.43.0
> 

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Re: [PATCH 4/5] drm/rockchip: dw_dp: Add DisplayPort support for rk3576

[Sebastian Reichel]

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Hi,

On Fri, Jan 09, 2026 at 04:00:47PM +0800, Andy Yan wrote:
> From: Andy Yan <andy.yan@rock-chips.com>
> 
> The DisplayPort of the RK3576 is basically the same as that of the
> RK3588, but it operates in dual-pixel mode and also support MST.
> 
> This patch only enable the SST output now.
> 
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---

Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com>

Greetings,

-- Sebastian

>  drivers/gpu/drm/rockchip/dw_dp-rockchip.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
> index 89d614d53596..dac3d202971e 100644
> --- a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
> @@ -142,10 +142,18 @@ static const struct dw_dp_plat_data rk3588_dp_plat_data = {
>  	.pixel_mode = DW_DP_MP_QUAD_PIXEL,
>  };
>  
> +static const struct dw_dp_plat_data rk3576_dp_plat_data = {
> +	.max_link_rate = 810000,
> +	.pixel_mode = DW_DP_MP_DUAL_PIXEL,
> +};
> +
>  static const struct of_device_id dw_dp_of_match[] = {
>  	{
>  		.compatible = "rockchip,rk3588-dp",
>  		.data = &rk3588_dp_plat_data,
> +	}, {
> +		.compatible = "rockchip,rk3576-dp",
> +		.data = &rk3576_dp_plat_data,
>  	},
>  	{}
>  };
> -- 
> 2.43.0
> 

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Re: [PATCH 5/5] arm64: dts: rockchip: Add DisplayPort dt node for rk3576

[Sebastian Reichel]

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Hi,

On Fri, Jan 09, 2026 at 04:00:48PM +0800, Andy Yan wrote:
> From: Andy Yan <andy.yan@rock-chips.com>
> 
> The DisplayPort on rk3576 is compliant with DisplayPort Specification
> Version 1.4 with MST support, and share the USBDP combo PHY with USB 3.1
> OTG0 controller.
> 
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---

Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com>

Greetings,

-- Sebastian

>  arch/arm64/boot/dts/rockchip/rk3576.dtsi | 28 ++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> index a86fc6b4e8c4..a153c3976cb3 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> @@ -1446,6 +1446,34 @@ hdmi_out: port@1 {
>  			};
>  		};
>  
> +		dp: dp@27e40000 {
> +			compatible = "rockchip,rk3576-dp";
> +			reg = <0x0 0x27e40000 0x0 0x30000>;
> +			interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
> +			assigned-clocks = <&cru CLK_AUX16MHZ_0>;
> +			assigned-clock-rates = <16000000>;
> +			clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16MHZ_0>,
> +				 <&cru ACLK_DP0>;
> +			clock-names = "apb", "aux", "hdcp";
> +			resets = <&cru SRST_DP0>;
> +			phys = <&usbdp_phy PHY_TYPE_DP>;
> +			power-domains = <&power RK3576_PD_VO1>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				dp0_in: port@0 {
> +					reg = <0>;
> +				};
> +
> +				dp0_out: port@1 {
> +					reg = <1>;
> +				};
> +			};
> +		};
> +
>  		sai7: sai@27ed0000 {
>  			compatible = "rockchip,rk3576-sai";
>  			reg = <0x0 0x27ed0000 0x0 0x1000>;
> -- 
> 2.43.0
> 

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Re: [PATCH 0/5] Add DisplayPort support for rk3576

[Sebastian Reichel]

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Hi,

On Fri, Jan 09, 2026 at 04:00:43PM +0800, Andy Yan wrote:
> From: Andy Yan <andy.yan@rock-chips.com>
> 
> The DisplayPort found on RK3576 is very similar to that of RK3588,
> but work in qual pixel mode and support for MST.
> 
> This patch series aims to add basic display output, not include
> audio and MST, which will be the work for the next stage.
> 
> Only test with 2 lane standard DP port output now.

This is a nice minimal series :) I got it working to some degree on
the RK3576 Sige5 USB-C port. The display connection detection is
_very_ unstable, but that part is handled by the TypeC Port Manager
and unrelated to the DP controller (and already an issue on the RK3588
based Rock 5B). IF the display is detected (i.e. USB-C side worked
properly), the DP controller managed to do proper output too. Thus
I believe this should be merged. I plan to look into the TCPM issues
in the meantime.

Greetings,

-- Sebastian

> 
> 
> 
> Andy Yan (5):
>   dt-bindings: display: rockchip: Add rk3576 DisplayPort
>   drm/bridge: synopsys: dw-dp: Set pixel mode by platform data
>   drm/bridge: synopsys: dw-dp: Make i2s/spdif clk optional
>   drm/rockchip: dw_dp: Add DisplayPort support for rk3576
>   arm64: dts: rockchip: Add DisplayPort dt node for rk3576
> 
>  .../display/rockchip/rockchip,dw-dp.yaml      | 29 +++++++++++++++++--
>  arch/arm64/boot/dts/rockchip/rk3576.dtsi      | 28 ++++++++++++++++++
>  drivers/gpu/drm/bridge/synopsys/dw-dp.c       | 12 ++------
>  drivers/gpu/drm/rockchip/dw_dp-rockchip.c     | 27 ++++++++++++++---
>  include/drm/bridge/dw_dp.h                    |  7 +++++
>  5 files changed, 87 insertions(+), 16 deletions(-)
> 
> -- 
> 2.43.0
> 
> base-commit: ad939ed1f8108513e84e93da90ad7ea31b56ef87
> branch: rk3576-dp-upstream
> 

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Re: [PATCH 0/5] Add DisplayPort support for rk3576

[Chaoyi Chen]

Hi Sebastian,

On 1/14/2026 5:51 AM, Sebastian Reichel wrote:
> Hi,
> 
> On Fri, Jan 09, 2026 at 04:00:43PM +0800, Andy Yan wrote:
>> From: Andy Yan <andy.yan@rock-chips.com>
>>
>> The DisplayPort found on RK3576 is very similar to that of RK3588,
>> but work in qual pixel mode and support for MST.
>>
>> This patch series aims to add basic display output, not include
>> audio and MST, which will be the work for the next stage.
>>
>> Only test with 2 lane standard DP port output now.
> 
> This is a nice minimal series :) I got it working to some degree on
> the RK3576 Sige5 USB-C port. The display connection detection is
> _very_ unstable, but that part is handled by the TypeC Port Manager
> and unrelated to the DP controller (and already an issue on the RK3588
> based Rock 5B). IF the display is detected (i.e. USB-C side worked
> properly), the DP controller managed to do proper output too. Thus
> I believe this should be merged. I plan to look into the TCPM issues
> in the meantime.

Based on experience with other platforms, I suspect that some HPD events
are not being properly propagated to the DP driver. This might be worth 
looking into.

-- 
Best, 
Chaoyi

Re: [PATCH 1/5] dt-bindings: display: rockchip: Add rk3576 DisplayPort

[Rob Herring]

On Tue, Jan 13, 2026 at 10:33:52PM +0100, Sebastian Reichel wrote:
> Hi,
> 
> On Fri, Jan 09, 2026 at 04:00:44PM +0800, Andy Yan wrote:
> > From: Andy Yan <andy.yan@rock-chips.com>
> > 
> > The DisplayPort found on RK3576 is very similar to that of RK3588,
> > but work in dual pixel mode. And itself does not depend on the I2S
> > clock or the SPDIF clock when transmit audio.
> > 
> > Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> > 
> > ---
> > 
> >  .../display/rockchip/rockchip,dw-dp.yaml      | 29 +++++++++++++++++--
> >  1 file changed, 26 insertions(+), 3 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
> > index 6345f0132d43..1bfe1bd6404a 100644
> > --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
> > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
> > @@ -27,13 +27,11 @@ description: |
> >    * Pixel clock up to 594MHz
> >    * I2S, SPDIF audio interface
> >  
> > -allOf:
> > -  - $ref: /schemas/sound/dai-common.yaml#
> > -
> >  properties:
> >    compatible:
> >      enum:
> >        - rockchip,rk3588-dp
> > +      - rockchip,rk3576-dp
> >  
> >    reg:
> >      maxItems: 1
> > @@ -42,6 +40,7 @@ properties:
> >      maxItems: 1
> >  
> >    clocks:
> > +    minItems: 3
> >      items:
> >        - description: Peripheral/APB bus clock
> >        - description: DisplayPort AUX clock
> > @@ -50,6 +49,7 @@ properties:
> >        - description: SPDIF interfce clock
> >  
> >    clock-names:
> > +    minItems: 3
> >      items:
> >        - const: apb
> >        - const: aux
> > @@ -95,6 +95,29 @@ required:
> >    - ports
> >    - resets
> >  
> > +allOf:
> > +  - $ref: /schemas/sound/dai-common.yaml#
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - rockchip,rk3588-dp
> > +    then:
> > +      properties:
> > +        clocks:
> > +          minItems: 5
> > +          maxItems: 5
> > +        clock-names:
> > +          minItems: 5
> > +          maxItems: 5
> 
> I think maxItems is not needed, since 6 items would not work for the
> specified items list anyways. Otherwise:

Correct.

Rob

Re: [PATCH 2/5] drm/bridge: synopsys: dw-dp: Set pixel mode by platform data

[Heiko Stuebner]

Am Freitag, 9. Januar 2026, 09:00:45 Mitteleuropäische Normalzeit schrieb Andy Yan:
> From: Andy Yan <andy.yan@rock-chips.com>
> 
> The DW DisplayPort hardware block can be configured to work in single,
> dual,quad pixel mode on differnt platforms, so make the pixel mode set
> by plat_data to support the upcoming rk3576 variant.
> 
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

While Dmitry helped a lot with looking at bridge drivers recently,
I think your recipient list does miss a number of other people
listed as bridge reviewers/maintainers.

$ scripts/get_maintainer.pl drivers/gpu/drm/bridge
Andrzej Hajda <andrzej.hajda@intel.com> (maintainer:DRM DRIVERS FOR BRIDGE CHIPS)
Neil Armstrong <neil.armstrong@linaro.org> (maintainer:DRM DRIVERS FOR BRIDGE CHIPS)
Robert Foss <rfoss@kernel.org> (maintainer:DRM DRIVERS FOR BRIDGE CHIPS)
Laurent Pinchart <Laurent.pinchart@ideasonboard.com> (reviewer:DRM DRIVERS FOR BRIDGE CHIPS)
Jonas Karlman <jonas@kwiboo.se> (reviewer:DRM DRIVERS FOR BRIDGE CHIPS)
Jernej Skrabec <jernej.skrabec@gmail.com> (reviewer:DRM DRIVERS FOR BRIDGE CHIPS)

As you'll need to do a v2 for the binding, please add the missing people
to the recipients.


For the change itself, can you improve the commit message a bit.

I assume the Single/Dual/Quad-Pixel config is a real hardware-feature
that is set when the IP is integrated into the soc? Or this a runtime
setting and a soc can support multiple output variants?


Thanks
Heiko