Re: [PATCH v4 5/7] iio: frequency: adf41513: features on frequency change

[Andy Shevchenko <andriy.shevchenko@intel.com>]

On Fri, Jan 16, 2026 at 02:32:24PM +0000, Rodrigo Alencar via B4 Relay wrote:

> Set Bleed current when PFD frequency changes (bleed enabled when in
> fractional mode). Set lock detector window size, handling bias and
> precision. Add phase resync support, setting clock dividers when
> PFD frequency changes.

...

> +static void adf41513_set_bleed_val(struct adf41513_state *st)
> +{
> +	u32 bleed_value;
> +
> +	if (st->data.phase_detector_polarity)
> +		bleed_value = 90;
> +	else
> +		bleed_value = 144;
> +
> +	bleed_value *= 1 + FIELD_GET(ADF41513_REG5_CP_CURRENT_MSK,
> +				     st->regs[ADF41513_REG5]);

I think it's better to have yet another temporary variable for this multiplier...

> +	bleed_value = div64_u64(st->settings.pfd_frequency_uhz * bleed_value,

...and here three operands instead.

	bleed_value = div64_u64(st->settings.pfd_frequency_uhz * curr * bleed_value,

> +				1600ULL * MEGA * MICROHZ_PER_HZ);
> +
> +	FIELD_MODIFY(ADF41513_REG6_BLEED_CURRENT_MSK, &st->regs[ADF41513_REG6],
> +		     bleed_value);
> +}
> +
> +static void adf41513_set_ld_window(struct adf41513_state *st)
> +{
> +	/*
> +	 * The ideal lock detector window size is halfway between the max
> +	 * window, set by the phase comparison period t_PFD = (1 / f_PFD),
> +	 * and the minimum is set by (I_BLEED/I_CP) × t_PFD
> +	 */
> +	u16 ld_window_10x_ns = div64_u64(10ULL * NSEC_PER_SEC * MICROHZ_PER_HZ,
> +					 st->settings.pfd_frequency_uhz << 1);

Okay, if we go this direction...

> +	u8 ld_idx, ldp, ld_bias;
> +
> +	if (st->settings.mode != ADF41513_MODE_INTEGER_N) {
> +		/* account for bleed current (deduced from eq.6 and eq.7) */
> +		if (st->data.phase_detector_polarity)
> +			ld_window_10x_ns += 4;
> +		else
> +			ld_window_10x_ns += 6;
> +	}
> +
> +	ld_idx = find_closest(ld_window_10x_ns, adf41513_ld_window_x10_ns,
> +			      ARRAY_SIZE(adf41513_ld_window_x10_ns));
> +	ldp = (adf41513_ldp_bias[ld_idx] >> 2) & 0x3;
> +	ld_bias = adf41513_ldp_bias[ld_idx] & 0x3;
> +
> +	FIELD_MODIFY(ADF41513_REG6_LDP_MSK, &st->regs[ADF41513_REG6], ldp);
> +	FIELD_MODIFY(ADF41513_REG9_LD_BIAS_MSK, &st->regs[ADF41513_REG9], ld_bias);
> +}
> +
> +static void adf41513_set_phase_resync(struct adf41513_state *st)
> +{
> +	u32 total_div, clk1_div, clk2_div;
> +
> +	if (!st->data.phase_resync_period_ns)
> +		return;
> +
> +	/* assuming both clock dividers hold similar values */
> +	total_div = mul_u64_u64_div_u64(st->settings.pfd_frequency_uhz,
> +					st->data.phase_resync_period_ns,
> +					1ULL * MICRO * NANO);

...for the consistency we may also use the same approach here

					1ULL * MICROHZ_PER_HZ * NSEC_PER_SEC);

At least it will be consistent with the annihilated units.

> +	clk1_div = clamp(int_sqrt(total_div), 1,
> +			 ADF41513_MAX_CLK_DIVIDER);
> +	clk2_div = clamp(DIV_ROUND_CLOSEST(total_div, clk1_div), 1,
> +			 ADF41513_MAX_CLK_DIVIDER);
> +
> +	FIELD_MODIFY(ADF41513_REG5_CLK1_DIV_MSK, &st->regs[ADF41513_REG5],
> +		     clk1_div);
> +	FIELD_MODIFY(ADF41513_REG7_CLK2_DIV_MSK, &st->regs[ADF41513_REG7],
> +		     clk2_div);
> +
> +	/* enable phase resync */
> +	st->regs[ADF41513_REG7] |= ADF41513_REG7_CLK_DIV_MODE_MSK;
> +}

-- 
With Best Regards,
Andy Shevchenko