From: Ben Zong-You Xie <ben717@andestech.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: <linux-i2c@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <andi.shyti@kernel.org>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>
Subject: Re: [PATCH 1/2] dt-bindings: i2c: add atciic100
Date: Thu, 22 Jan 2026 19:18:27 +0800 [thread overview]
Message-ID: <aXIHg59ZZouB9WMl@ANB420.andestech.com> (raw)
In-Reply-To: <20250209-antique-camel-of-assurance-390cb9@krzk-bin>
On Sun, Feb 09, 2025 at 01:29:58PM +0100, Krzysztof Kozlowski wrote:
> On Fri, Feb 07, 2025 at 10:19:22AM +0800, Ben Zong-You Xie wrote:
> > Document devicetree bindings for Andes I2C controller.
>
> Explain what is the hardware... Here is Andes I2C
>
> >
> > Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> > ---
> > .../bindings/i2c/andestech,i2c-atciic100.yaml | 40 +++++++++++++++++++
> > MAINTAINERS | 5 +++
> > 2 files changed, 45 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/i2c/andestech,i2c-atciic100.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/i2c/andestech,i2c-atciic100.yaml b/Documentation/devicetree/bindings/i2c/andestech,i2c-atciic100.yaml
> > new file mode 100644
> > index 000000000000..cf96a9186176
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/i2c/andestech,i2c-atciic100.yaml
> > @@ -0,0 +1,40 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pwm/andestech,atciic100.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Andes I2C Controller
>
> Here as well
>
> > +
> > +maintainers:
> > + - Ben Zong-You Xie <ben717@andestech.com>
> > +
> > +allOf:
> > + - $ref: /schemas/i2c/i2c-controller.yaml#
> > +
> > +properties:
> > + compatible:
> > + const: andestech,atciic100
>
> But here atciic100. This is all confusing. What is the SoC? What is the
> name of this device?
Hi Krzysztof,
Sorry for the confusion. atciic100 is the name for the I2C IP block, and it
is integrated on QiLai SoC. That's why I added a new compatible
"andestech,qilai-i2c" in v2.
For AE350 platform, I know it has not been upstreamed yet, but it was
discussed and acknowledged in a separate SPI series [1], which is why I
included it as a fallback. Can I keep this? If not, I will drop it
and update the compatibles in v3 as follows:
properties:
compatible:
const: andestech,qilai-i2c
[1] https://lore.kernel.org/linux-spi/20251210-repeated-perjurer-99219893524a@spud/
Thanks,
Ben
next prev parent reply other threads:[~2026-01-22 11:20 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-07 2:19 [PATCH 0/2] i2c: add I2C driver for Andes atciic100 Ben Zong-You Xie
2025-02-07 2:19 ` [PATCH 1/2] dt-bindings: i2c: add atciic100 Ben Zong-You Xie
2025-02-07 3:23 ` Rob Herring (Arm)
2025-02-07 5:57 ` Ben Zong-You Xie
2025-02-09 12:29 ` Krzysztof Kozlowski
2026-01-22 11:18 ` Ben Zong-You Xie [this message]
2026-01-22 11:27 ` Krzysztof Kozlowski
2026-01-22 13:59 ` Ben Zong-You Xie
2025-02-07 2:19 ` [PATCH 2/2] i2c: atciic100: add Andes I2C driver support Ben Zong-You Xie
2025-03-20 10:44 ` Andi Shyti
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