[PATCH] MIPS: Loongson64: dts: fix phy-related definition of LS7A GMAC

[PATCH] MIPS: Loongson64: dts: fix phy-related definition of LS7A GMAC

[Icenowy Zheng]

Currently the LS7A GMAC device tree node lacks a proper phy-handle
property pointing to the PHY node.

In addition, the phy-mode property specifies "rgmii" without any
internal delay information, which means the board trace needs to add 2ns
delay to the RGMII data lines; but that isn't known to happen on any
Loongson board. The ACPI-based initialization codepath, which is used on
LoongArch-based 3A5000 + 7A1000 hardwares, specifies "rgmii-id" phy
mode, which should be the one we are using.

Add the lacking phy-handle property and set proper phy-mode.

Tested on a LS3A4000_7A1000_NUC_BOARD_V2.1 board with YT8521S PHY.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
index ee71045883e7e..6dee85909f5a6 100644
--- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -199,7 +199,8 @@ gmac@3,0 {
 					     <13 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names = "macirq", "eth_lpi";
 				interrupt-parent = <&pic>;
-				phy-mode = "rgmii";
+				phy-mode = "rgmii-id";
+				phy-handle = <&phy0>;
 				mdio {
 					#address-cells = <1>;
 					#size-cells = <0>;
@@ -222,7 +223,8 @@ gmac@3,1 {
 					     <15 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names = "macirq", "eth_lpi";
 				interrupt-parent = <&pic>;
-				phy-mode = "rgmii";
+				phy-mode = "rgmii-id";
+				phy-handle = <&phy1>;
 				mdio {
 					#address-cells = <1>;
 					#size-cells = <0>;
-- 
2.52.0

Re: [PATCH] MIPS: Loongson64: dts: fix phy-related definition of LS7A GMAC

[Jiaxun Yang]

On Fri, 2 Jan 2026, at 3:52 PM, Icenowy Zheng wrote:
> Currently the LS7A GMAC device tree node lacks a proper phy-handle
> property pointing to the PHY node.
>
> In addition, the phy-mode property specifies "rgmii" without any
> internal delay information, which means the board trace needs to add 2ns
> delay to the RGMII data lines; but that isn't known to happen on any
> Loongson board. The ACPI-based initialization codepath, which is used on
> LoongArch-based 3A5000 + 7A1000 hardwares, specifies "rgmii-id" phy
> mode, which should be the one we are using.
>
> Add the lacking phy-handle property and set proper phy-mode.
>
> Tested on a LS3A4000_7A1000_NUC_BOARD_V2.1 board with YT8521S PHY.
>
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>

Good catch! This with fine with realtek phy chips but YT8521S seems
to be picky.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Also maybe:

Cc: stable@vger.kernel.org

Given those boards rely on built-in DT.

Thanks

> ---
>  arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi 
> b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
> index ee71045883e7e..6dee85909f5a6 100644
> --- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
> +++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
> @@ -199,7 +199,8 @@ gmac@3,0 {
>  					     <13 IRQ_TYPE_LEVEL_HIGH>;
>  				interrupt-names = "macirq", "eth_lpi";
>  				interrupt-parent = <&pic>;
> -				phy-mode = "rgmii";
> +				phy-mode = "rgmii-id";
> +				phy-handle = <&phy0>;
>  				mdio {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
> @@ -222,7 +223,8 @@ gmac@3,1 {
>  					     <15 IRQ_TYPE_LEVEL_HIGH>;
>  				interrupt-names = "macirq", "eth_lpi";
>  				interrupt-parent = <&pic>;
> -				phy-mode = "rgmii";
> +				phy-mode = "rgmii-id";
> +				phy-handle = <&phy1>;
>  				mdio {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
> -- 
> 2.52.0

-- 
- Jiaxun

Re: [PATCH] MIPS: Loongson64: dts: fix phy-related definition of LS7A GMAC

[Icenowy Zheng]

在 2026-01-02星期五的 22:36 +0000，Jiaxun Yang写道：
> 
> 
> On Fri, 2 Jan 2026, at 3:52 PM, Icenowy Zheng wrote:
> > Currently the LS7A GMAC device tree node lacks a proper phy-handle
> > property pointing to the PHY node.
> > 
> > In addition, the phy-mode property specifies "rgmii" without any
> > internal delay information, which means the board trace needs to
> > add 2ns
> > delay to the RGMII data lines; but that isn't known to happen on
> > any
> > Loongson board. The ACPI-based initialization codepath, which is
> > used on
> > LoongArch-based 3A5000 + 7A1000 hardwares, specifies "rgmii-id" phy
> > mode, which should be the one we are using.
> > 
> > Add the lacking phy-handle property and set proper phy-mode.
> > 
> > Tested on a LS3A4000_7A1000_NUC_BOARD_V2.1 board with YT8521S PHY.
> > 
> > Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> 
> Good catch! This with fine with realtek phy chips but YT8521S seems
> to be picky.

I think they might not work with Realtek PHYs now either, considering
delay override code for RTL8211E/F entered mainline Realtek PHY driver.
(Previously it just ignores the phy-mode internal delay information and
rely on what its strap pin defines)

> 
> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> 
> Also maybe:
> 
> Cc: stable@vger.kernel.org
> 
> Given those boards rely on built-in DT.
> 
> Thanks
> 
> > ---
> >  arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi 
> > b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
> > index ee71045883e7e..6dee85909f5a6 100644
> > --- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
> > +++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
> > @@ -199,7 +199,8 @@ gmac@3,0 {
> >                                              <13
> > IRQ_TYPE_LEVEL_HIGH>;
> >                                 interrupt-names = "macirq",
> > "eth_lpi";
> >                                 interrupt-parent = <&pic>;
> > -                               phy-mode = "rgmii";
> > +                               phy-mode = "rgmii-id";
> > +                               phy-handle = <&phy0>;
> >                                 mdio {
> >                                         #address-cells = <1>;
> >                                         #size-cells = <0>;
> > @@ -222,7 +223,8 @@ gmac@3,1 {
> >                                              <15
> > IRQ_TYPE_LEVEL_HIGH>;
> >                                 interrupt-names = "macirq",
> > "eth_lpi";
> >                                 interrupt-parent = <&pic>;
> > -                               phy-mode = "rgmii";
> > +                               phy-mode = "rgmii-id";
> > +                               phy-handle = <&phy1>;
> >                                 mdio {
> >                                         #address-cells = <1>;
> >                                         #size-cells = <0>;
> > -- 
> > 2.52.0
> 

Re: [PATCH] MIPS: Loongson64: dts: fix phy-related definition of LS7A GMAC

[Thomas Bogendoerfer]

On Fri, Jan 02, 2026 at 11:52:43PM +0800, Icenowy Zheng wrote:
> Currently the LS7A GMAC device tree node lacks a proper phy-handle
> property pointing to the PHY node.
> 
> In addition, the phy-mode property specifies "rgmii" without any
> internal delay information, which means the board trace needs to add 2ns
> delay to the RGMII data lines; but that isn't known to happen on any
> Loongson board. The ACPI-based initialization codepath, which is used on
> LoongArch-based 3A5000 + 7A1000 hardwares, specifies "rgmii-id" phy
> mode, which should be the one we are using.
> 
> Add the lacking phy-handle property and set proper phy-mode.
> 
> Tested on a LS3A4000_7A1000_NUC_BOARD_V2.1 board with YT8521S PHY.
> 
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> ---
>  arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
> index ee71045883e7e..6dee85909f5a6 100644
> --- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
> +++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
> @@ -199,7 +199,8 @@ gmac@3,0 {
>  					     <13 IRQ_TYPE_LEVEL_HIGH>;
>  				interrupt-names = "macirq", "eth_lpi";
>  				interrupt-parent = <&pic>;
> -				phy-mode = "rgmii";
> +				phy-mode = "rgmii-id";
> +				phy-handle = <&phy0>;
>  				mdio {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
> @@ -222,7 +223,8 @@ gmac@3,1 {
>  					     <15 IRQ_TYPE_LEVEL_HIGH>;
>  				interrupt-names = "macirq", "eth_lpi";
>  				interrupt-parent = <&pic>;
> -				phy-mode = "rgmii";
> +				phy-mode = "rgmii-id";
> +				phy-handle = <&phy1>;
>  				mdio {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
> -- 
> 2.52.0

applied to mips-next
Thomas.

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