Re: [PATCH v2 0/4] iio: adc: ad4080: add support for AD4880 dual-channel ADC

[Andy Shevchenko <andriy.shevchenko@intel.com>]

On Sat, Feb 14, 2026 at 04:08:52PM +0000, Jonathan Cameron wrote:
> On Sun, 8 Feb 2026 14:50:23 +0200
> Andy Shevchenko <andriy.shevchenko@intel.com> wrote:
> > On Fri, Feb 06, 2026 at 06:07:12PM +0200, Antoniu Miclaus wrote:

...

> > I believe there is a better approach, what you need is rather a flag
> > to SPI core to tell that this is the device with shared CS.
> 
> Antoniu, this comment from Andy needs addressing before we move
> on. It seems fairly fundamental and I'm not seeing a reply to it on list.
> 
> I'm not entirely sure what Andy is suggesting will work but this
> is perhaps a mismatch in really understanding what is going on here.
> Andy, how would a flag work given they seem to be separately addressable
> SPI buses. I think this isn't a shared SPI CS, but rather a device
> with two entirely separate SPI buses. I think the only reason
> we are bothering to implement it as a single device at all is the
> shared backend.

My understanding that there are two devices that for whatever reason share
the same CS line. Yes, I probably misread the idea behind, but I meant
some flag for SPI device that tells SPI core that the CS it wants is shared
(maybe a high bit in the cs field or so), then CS core won't complain on
validation about using the same cs number which is "already in use".

> There is an argument that maybe we should be looking at how
> to do data muxing backends to support the more general case of two
> separate chips feeding into a single buffer, but that's a complex
> beast and I'm not sure if it is something we actually need.

Yeah, if possible I prefer to look at the (ASCII art) schematics
on how the HW looks like (connections with busses and CS lines).

-- 
With Best Regards,
Andy Shevchenko