* Re: [PATCH v3] arm64: dts: qcom: sa8540p-ride: enable PCIe support
2022-12-02 12:09 [PATCH v3] arm64: dts: qcom: sa8540p-ride: enable PCIe support Brian Masney
@ 2022-12-02 20:43 ` Andrew Halaney
2022-12-06 13:50 ` Shazad Hussain
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Andrew Halaney @ 2022-12-02 20:43 UTC (permalink / raw)
To: Brian Masney
Cc: andersson, krzysztof.kozlowski+dt, agross, konrad.dybcio, robh+dt,
linux-arm-msm, devicetree, linux-kernel, quic_shazhuss, psodagud,
echanude
On Fri, Dec 02, 2022 at 07:09:18AM -0500, Brian Masney wrote:
> Add the vreg_l11a, pcie3a, pcie3a_phy, and tlmm nodes that are necessary
> in order to get PCIe working on the QDrive3.
>
> This patch also increases the width of the ranges property for the PCIe
> switch that's found on this platform. Note that this change requires
> the latest trustzone (TZ) firmware that's available from Qualcomm as
> of November 2022. If this is used against a board with the older
> firmware, then the board will go into ramdump mode when PCIe is probed
> on startup.
>
> The ranges property is overridden in this sa8540p-ride.dts file since
> this is what's used to describe the QDrive3 variant with dual SoCs.
> There's another variant of this board that only has a single SoC where
> this change is not applicable, and hence why this specific change was
> not done in sa8540p.dtsi.
>
> These changes were derived from various patches that Qualcomm
> delivered to Red Hat in a downstream kernel.
>
> Signed-off-by: Brian Masney <bmasney@redhat.com>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
PCIe on the 2 sips on the qdrive3 (sa8540p-ride) I have seems to be
working with this patch applied, thanks!
> ---
> Changes since v2:
> - Dropped regulator-allow-set-load (Bjorn)
> - Updated first member of ranges property to match downstream:
> s/0x32200000/0x40200000/ (Andrew)
>
> Changes since v1:
> - Add -state and -pins suffixes to tlmm (Krzysztof)
>
> This patch depends on the following series that hasn't made it's way
> into linux-next yet:
>
> [PATCH v10 0/2] arm64: dts: qcom: add dts for sa8540p-ride board
> https://lore.kernel.org/lkml/20221118025158.16902-1-quic_ppareek@quicinc.com/
>
> I can't find the specific TZ firmware version that we have so that's why
> I included the date instead.
>
> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 53 +++++++++++++++++++++++
> 1 file changed, 53 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> index a5f87a8629d6..a638e3784543 100644
> --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> @@ -51,6 +51,13 @@ vreg_l7a: ldo7 {
> regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> };
>
> + vreg_l11a: ldo11 {
> + regulator-name = "vreg_l11a";
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <880000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> vreg_l13a: ldo13 {
> regulator-name = "vreg_l13a";
> regulator-min-microvolt = <3072000>;
> @@ -139,6 +146,27 @@ vreg_l8g: ldo8 {
> };
> };
>
> +&pcie3a {
> + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>,
> + <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>;
> +
> + perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie3a_default>;
> +
> + status = "okay";
> +};
> +
> +&pcie3a_phy {
> + vdda-phy-supply = <&vreg_l11a>;
> + vdda-pll-supply = <&vreg_l3a>;
> +
> + status = "okay";
> +};
> +
> &qup2 {
> status = "okay";
> };
> @@ -158,6 +186,31 @@ &remoteproc_nsp1 {
> status = "okay";
> };
>
> +&tlmm {
> + pcie3a_default: pcie3a-default-state {
> + perst-pins {
> + pins = "gpio151";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + clkreq-pins {
> + pins = "gpio150";
> + function = "pcie3a_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + wake-pins {
> + pins = "gpio56";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +};
> +
> &ufs_mem_hc {
> reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
>
> --
> 2.38.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v3] arm64: dts: qcom: sa8540p-ride: enable PCIe support
2022-12-02 12:09 [PATCH v3] arm64: dts: qcom: sa8540p-ride: enable PCIe support Brian Masney
2022-12-02 20:43 ` Andrew Halaney
@ 2022-12-06 13:50 ` Shazad Hussain
2022-12-06 15:50 ` Johan Hovold
2022-12-06 18:18 ` Bjorn Andersson
3 siblings, 0 replies; 5+ messages in thread
From: Shazad Hussain @ 2022-12-06 13:50 UTC (permalink / raw)
To: Brian Masney, andersson, krzysztof.kozlowski+dt
Cc: agross, konrad.dybcio, robh+dt, linux-arm-msm, devicetree,
linux-kernel, psodagud, ahalaney, echanude
On 12/2/2022 5:39 PM, Brian Masney wrote:
> Add the vreg_l11a, pcie3a, pcie3a_phy, and tlmm nodes that are necessary
> in order to get PCIe working on the QDrive3.
>
> This patch also increases the width of the ranges property for the PCIe
> switch that's found on this platform. Note that this change requires
> the latest trustzone (TZ) firmware that's available from Qualcomm as
> of November 2022. If this is used against a board with the older
> firmware, then the board will go into ramdump mode when PCIe is probed
> on startup.
>
> The ranges property is overridden in this sa8540p-ride.dts file since
> this is what's used to describe the QDrive3 variant with dual SoCs.
> There's another variant of this board that only has a single SoC where
> this change is not applicable, and hence why this specific change was
> not done in sa8540p.dtsi.
>
> These changes were derived from various patches that Qualcomm
> delivered to Red Hat in a downstream kernel.
>
> Signed-off-by: Brian Masney <bmasney@redhat.com>
Tested-by: Shazad Hussain <quic_shazhuss@quicinc.com>
This patch seems to work on both SOC1 and SOC2 for qdrive3
(sa8540p-ride) board.
-Shazad
> ---
> Changes since v2:
> - Dropped regulator-allow-set-load (Bjorn)
> - Updated first member of ranges property to match downstream:
> s/0x32200000/0x40200000/ (Andrew)
>
> Changes since v1:
> - Add -state and -pins suffixes to tlmm (Krzysztof)
>
> This patch depends on the following series that hasn't made it's way
> into linux-next yet:
>
> [PATCH v10 0/2] arm64: dts: qcom: add dts for sa8540p-ride board
> https://lore.kernel.org/lkml/20221118025158.16902-1-quic_ppareek@quicinc.com/
>
> I can't find the specific TZ firmware version that we have so that's why
> I included the date instead.
>
> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 53 +++++++++++++++++++++++
> 1 file changed, 53 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> index a5f87a8629d6..a638e3784543 100644
> --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> @@ -51,6 +51,13 @@ vreg_l7a: ldo7 {
> regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> };
>
> + vreg_l11a: ldo11 {
> + regulator-name = "vreg_l11a";
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <880000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> vreg_l13a: ldo13 {
> regulator-name = "vreg_l13a";
> regulator-min-microvolt = <3072000>;
> @@ -139,6 +146,27 @@ vreg_l8g: ldo8 {
> };
> };
>
> +&pcie3a {
> + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>,
> + <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>;
> +
> + perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie3a_default>;
> +
> + status = "okay";
> +};
> +
> +&pcie3a_phy {
> + vdda-phy-supply = <&vreg_l11a>;
> + vdda-pll-supply = <&vreg_l3a>;
> +
> + status = "okay";
> +};
> +
> &qup2 {
> status = "okay";
> };
> @@ -158,6 +186,31 @@ &remoteproc_nsp1 {
> status = "okay";
> };
>
> +&tlmm {
> + pcie3a_default: pcie3a-default-state {
> + perst-pins {
> + pins = "gpio151";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + clkreq-pins {
> + pins = "gpio150";
> + function = "pcie3a_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + wake-pins {
> + pins = "gpio56";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +};
> +
> &ufs_mem_hc {
> reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v3] arm64: dts: qcom: sa8540p-ride: enable PCIe support
2022-12-02 12:09 [PATCH v3] arm64: dts: qcom: sa8540p-ride: enable PCIe support Brian Masney
2022-12-02 20:43 ` Andrew Halaney
2022-12-06 13:50 ` Shazad Hussain
@ 2022-12-06 15:50 ` Johan Hovold
2022-12-06 18:18 ` Bjorn Andersson
3 siblings, 0 replies; 5+ messages in thread
From: Johan Hovold @ 2022-12-06 15:50 UTC (permalink / raw)
To: Brian Masney
Cc: andersson, krzysztof.kozlowski+dt, agross, konrad.dybcio, robh+dt,
linux-arm-msm, devicetree, linux-kernel, quic_shazhuss, psodagud,
ahalaney, echanude
On Fri, Dec 02, 2022 at 07:09:18AM -0500, Brian Masney wrote:
> Add the vreg_l11a, pcie3a, pcie3a_phy, and tlmm nodes that are necessary
> in order to get PCIe working on the QDrive3.
> @@ -158,6 +186,31 @@ &remoteproc_nsp1 {
> status = "okay";
> };
>
> +&tlmm {
> + pcie3a_default: pcie3a-default-state {
> + perst-pins {
> + pins = "gpio151";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + clkreq-pins {
> + pins = "gpio150";
> + function = "pcie3a_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + wake-pins {
> + pins = "gpio56";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +};
> +
The pin configuration nodes typically go last after a
/* PINCTRL */
delimiter as this section tends to become rather long.
> &ufs_mem_hc {
> reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
Johan
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v3] arm64: dts: qcom: sa8540p-ride: enable PCIe support
2022-12-02 12:09 [PATCH v3] arm64: dts: qcom: sa8540p-ride: enable PCIe support Brian Masney
` (2 preceding siblings ...)
2022-12-06 15:50 ` Johan Hovold
@ 2022-12-06 18:18 ` Bjorn Andersson
3 siblings, 0 replies; 5+ messages in thread
From: Bjorn Andersson @ 2022-12-06 18:18 UTC (permalink / raw)
To: bmasney, krzysztof.kozlowski+dt
Cc: robh+dt, psodagud, quic_shazhuss, echanude, linux-arm-msm,
linux-kernel, devicetree, konrad.dybcio, agross, ahalaney
On Fri, 2 Dec 2022 07:09:18 -0500, Brian Masney wrote:
> Add the vreg_l11a, pcie3a, pcie3a_phy, and tlmm nodes that are necessary
> in order to get PCIe working on the QDrive3.
>
> This patch also increases the width of the ranges property for the PCIe
> switch that's found on this platform. Note that this change requires
> the latest trustzone (TZ) firmware that's available from Qualcomm as
> of November 2022. If this is used against a board with the older
> firmware, then the board will go into ramdump mode when PCIe is probed
> on startup.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: qcom: sa8540p-ride: enable PCIe support
commit: b8bf63f8eb728dc9cb0ae0ee921eb889a11186cb
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 5+ messages in thread