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From: Kris Chaplin <kris.chaplin@amd.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Conor Dooley <conor@kernel.org>
Cc: thomas.delev@amd.com, michal.simek@amd.com, robh+dt@kernel.org,
	conor+dt@kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, git@amd.com
Subject: Re: [PATCH 1/2] dt-bindings: w1: Add YAML DT Schema for AMD w1 master and MAINTAINERS entry
Date: Fri, 13 Oct 2023 16:36:06 +0100	[thread overview]
Message-ID: <aa66b946-8d97-db50-bc3b-7f1694de2cda@amd.com> (raw)
In-Reply-To: <6fa74ee3-a2ef-4d76-964f-51249f53cbaa@linaro.org>

On 13/10/2023 16:29, Krzysztof Kozlowski wrote:
>
> AMD product managers are highly skilled in naming things. Sigh.
>
> Go ahead with AXI 1-wire master. Any future - from now to next 100 years
> - product from AMD which will be different but sold under the same name,
> thus creating conflict in compatible naming, should be rejected because
> of that conflict or renamed to something else. If that happen I will
> propose a name like "banana-wire".
>
> Best regards,
> Krzysztof

To be fair on the product managers the IP naming from a hardware 
perspective is in the context of the ex-Xilinx development tools, and as 
such there is no risk of namespace overlap with the rest of the 
business.  I'm not against changing the binding name for clarity in the 
kernel. Would adding pl within the binding (Programmable Logic) assist? 
Ie: amd,pl-axi-1wire-master

Regards
Kris




  reply	other threads:[~2023-10-13 15:36 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-13  9:30 [PATCH 0/2] w1: Add 1-wire master driver for AMD programmable logic IP Core Kris Chaplin
2023-10-13  9:30 ` [PATCH 1/2] dt-bindings: w1: Add YAML DT Schema for AMD w1 master and MAINTAINERS entry Kris Chaplin
2023-10-13 15:01   ` Conor Dooley
2023-10-13 15:04   ` Krzysztof Kozlowski
2023-10-13 15:07     ` Conor Dooley
2023-10-13 15:22       ` Krzysztof Kozlowski
2023-10-13 15:23       ` Kris Chaplin
2023-10-13 15:29         ` Krzysztof Kozlowski
2023-10-13 15:36           ` Kris Chaplin [this message]
2023-10-13 17:18         ` Rob Herring
2023-10-13 17:58           ` Kris Chaplin
2023-10-13  9:30 ` [PATCH 2/2] w1: Add 1-wire master driver for AMD programmable logic IP Core Kris Chaplin
2023-10-13 15:20   ` Krzysztof Kozlowski
2023-10-18 15:54     ` Kris Chaplin
2023-10-18 16:00       ` Krzysztof Kozlowski
2023-10-19 14:24 ` [PATCH v2 0/2] w1: Add AXI 1-wire host driver for AMD programmable logic IP core Kris Chaplin
2023-10-19 14:24   ` [PATCH v2 1/2] dt-bindings: w1: Add YAML DT schema for AMD AXI w1 host and MAINTAINERS entry Kris Chaplin
2023-10-19 14:30     ` Conor Dooley
2023-10-19 14:35       ` Michal Simek
2023-10-19 14:39         ` Kris Chaplin
2023-10-19 14:24   ` [PATCH v2 2/2] w1: Add AXI 1-wire host driver for AMD programmable logic IP core Kris Chaplin
2023-10-19 14:28   ` [PATCH v2 0/2] " Conor Dooley

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