From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A412C43334 for ; Mon, 13 Jun 2022 05:32:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230215AbiFMFcn (ORCPT ); Mon, 13 Jun 2022 01:32:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230308AbiFMFcl (ORCPT ); Mon, 13 Jun 2022 01:32:41 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BDEA1032; Sun, 12 Jun 2022 22:32:39 -0700 (PDT) X-UUID: bc1d8f81d4cc4ad0a682904ebf31f49a-20220613 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:ffedf2af-c1b3-4263-9c21-41511bb22f4f,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:a05357c6-12ba-4305-bfdf-9aefbdc32516,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: bc1d8f81d4cc4ad0a682904ebf31f49a-20220613 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 814096980; Mon, 13 Jun 2022 13:32:30 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 13 Jun 2022 13:32:29 +0800 Received: from mhfsdcap04 (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 13 Jun 2022 13:32:28 +0800 Message-ID: Subject: Re: [PATCH v3 2/3] iommu: mtk_iommu: Introduce new flag TF_PORT_TO_ADDR_MT8173 From: Yong Wu To: AngeloGioacchino Del Regno CC: , , , , , , , , , , , , , <~postmarketos/upstreaming@lists.sr.ht>, , Date: Mon, 13 Jun 2022 13:32:28 +0800 In-Reply-To: <20220609104001.97753-3-angelogioacchino.delregno@collabora.com> References: <20220609104001.97753-1-angelogioacchino.delregno@collabora.com> <20220609104001.97753-3-angelogioacchino.delregno@collabora.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, 2022-06-09 at 12:40 +0200, AngeloGioacchino Del Regno wrote: > In preparation for adding support for MT6795, add a new flag named > TF_PORT_TO_ADDR_MT8173 and use that instead of checking for m4u_plat > type in mtk_iommu_hw_init() to avoid seeing a long list of m4u_plat > checks there in the future. > > Signed-off-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> Retitle to: iommu/mediatek: Xxx, then Reviewed-by: Yong Wu > --- > drivers/iommu/mtk_iommu.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 0ea0848581e9..8611cf8e4bd5 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -140,6 +140,7 @@ > #define IFA_IOMMU_PCIE_SUPPORT BIT(16) > /* IOMMU I/O (r/w) is enabled using PERICFG_IOMMU_1 register */ > #define HAS_PERI_IOMMU1_REG BIT(17) > +#define TF_PORT_TO_ADDR_MT8173 BIT(18) > > #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ > ((((pdata)->flags) & (mask)) == (_x)) > @@ -960,7 +961,7 @@ static int mtk_iommu_hw_init(const struct > mtk_iommu_data *data, unsigned int ban > * Global control settings are in bank0. May re-init these > global registers > * since no sure if there is bank0 consumers. > */ > - if (data->plat_data->m4u_plat == M4U_MT8173) { > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, > TF_PORT_TO_ADDR_MT8173)) { > regval = F_MMU_PREFETCH_RT_REPLACE_MOD | > F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; > } else { > @@ -1437,7 +1438,8 @@ static const struct mtk_iommu_plat_data > mt8167_data = { > static const struct mtk_iommu_plat_data mt8173_data = { > .m4u_plat = M4U_MT8173, > .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | > - HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, > + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | > + TF_PORT_TO_ADDR_MT8173, > .inv_sel_reg = REG_MMU_INV_SEL_GEN1, > .banks_num = 1, > .banks_enable = {true},