* [PATCH v3 0/3] MediaTek Helio X10 MT6795 - M4U/IOMMU Support
@ 2022-06-09 10:39 AngeloGioacchino Del Regno
2022-06-09 10:39 ` [PATCH v3 1/3] dt-bindings: mediatek: Add bindings for MT6795 M4U AngeloGioacchino Del Regno
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-06-09 10:39 UTC (permalink / raw)
To: yong.wu
Cc: joro, will, robh+dt, krzysztof.kozlowski+dt, matthias.bgg, iommu,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
konrad.dybcio, marijn.suijten, martin.botka,
~postmarketos/upstreaming, phone-devel, paul.bouchara,
AngeloGioacchino Del Regno
In an effort to give some love to the apparently forgotten MT6795 SoC,
I am upstreaming more components that are necessary to support platforms
powered by this one apart from a simple boot to serial console.
This series introduces support for the IOMMUs found on this SoC.
Tested on a MT6795 Sony Xperia M5 (codename "Holly") smartphone.
Changes in v3:
- Added new flag as suggested by Yong Wu
- Rebased on top of https://patchwork.kernel.org/project/linux-mediatek/list/?series=648784
Changes in v2:
- Rebased on top of https://patchwork.kernel.org/project/linux-mediatek/list/?series=642681
AngeloGioacchino Del Regno (3):
dt-bindings: mediatek: Add bindings for MT6795 M4U
iommu: mtk_iommu: Introduce new flag TF_PORT_TO_ADDR_MT8173
iommu: mtk_iommu: Add support for MT6795 Helio X10 M4Us
.../bindings/iommu/mediatek,iommu.yaml | 4 +
drivers/iommu/mtk_iommu.c | 21 +++-
include/dt-bindings/memory/mt6795-larb-port.h | 96 +++++++++++++++++++
3 files changed, 119 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/memory/mt6795-larb-port.h
--
2.35.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v3 1/3] dt-bindings: mediatek: Add bindings for MT6795 M4U 2022-06-09 10:39 [PATCH v3 0/3] MediaTek Helio X10 MT6795 - M4U/IOMMU Support AngeloGioacchino Del Regno @ 2022-06-09 10:39 ` AngeloGioacchino Del Regno 2022-06-13 5:32 ` Yong Wu 2022-06-09 10:40 ` [PATCH v3 2/3] iommu: mtk_iommu: Introduce new flag TF_PORT_TO_ADDR_MT8173 AngeloGioacchino Del Regno 2022-06-09 10:40 ` [PATCH v3 3/3] iommu: mtk_iommu: Add support for MT6795 Helio X10 M4Us AngeloGioacchino Del Regno 2 siblings, 1 reply; 7+ messages in thread From: AngeloGioacchino Del Regno @ 2022-06-09 10:39 UTC (permalink / raw) To: yong.wu Cc: joro, will, robh+dt, krzysztof.kozlowski+dt, matthias.bgg, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, konrad.dybcio, marijn.suijten, martin.botka, ~postmarketos/upstreaming, phone-devel, paul.bouchara, AngeloGioacchino Del Regno, Rob Herring Add bindings for the MediaTek Helio X10 (MT6795) IOMMU/M4U. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> --- .../bindings/iommu/mediatek,iommu.yaml | 4 + include/dt-bindings/memory/mt6795-larb-port.h | 96 +++++++++++++++++++ 2 files changed, 100 insertions(+) create mode 100644 include/dt-bindings/memory/mt6795-larb-port.h diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index d5e3272a54e8..20902c387520 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -73,6 +73,7 @@ properties: - mediatek,mt2701-m4u # generation one - mediatek,mt2712-m4u # generation two - mediatek,mt6779-m4u # generation two + - mediatek,mt6795-m4u # generation two - mediatek,mt8167-m4u # generation two - mediatek,mt8173-m4u # generation two - mediatek,mt8183-m4u # generation two @@ -128,6 +129,7 @@ properties: dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, dt-binding/memory/mt2712-larb-port.h for mt2712, dt-binding/memory/mt6779-larb-port.h for mt6779, + dt-binding/memory/mt6795-larb-port.h for mt6795, dt-binding/memory/mt8167-larb-port.h for mt8167, dt-binding/memory/mt8173-larb-port.h for mt8173, dt-binding/memory/mt8183-larb-port.h for mt8183, @@ -152,6 +154,7 @@ allOf: enum: - mediatek,mt2701-m4u - mediatek,mt2712-m4u + - mediatek,mt6795-m4u - mediatek,mt8173-m4u - mediatek,mt8186-iommu-mm - mediatek,mt8192-m4u @@ -181,6 +184,7 @@ allOf: contains: enum: - mediatek,mt2712-m4u + - mediatek,mt6795-m4u - mediatek,mt8173-m4u then: diff --git a/include/dt-bindings/memory/mt6795-larb-port.h b/include/dt-bindings/memory/mt6795-larb-port.h new file mode 100644 index 000000000000..223aca8fd350 --- /dev/null +++ b/include/dt-bindings/memory/mt6795-larb-port.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#ifndef _DT_BINDINGS_MEMORY_MT6795_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT6795_LARB_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 +#define M4U_LARB3_ID 3 +#define M4U_LARB4_ID 4 +#define M4U_LARB5_ID 5 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 7) +#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 8) +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 9) +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 10) +#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 11) +#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 12) +#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 13) + +/* larb1 */ +#define M4U_PORT_VDEC_MC MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_VDEC_PP MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_VDEC_UFO MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_VDEC_VLD MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_VDEC_VLD2 MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_VDEC_AVC_MV MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_VDEC_PRED_RD MTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_VDEC_PRED_WR MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_VDEC_PPWRAP MTK_M4U_ID(M4U_LARB1_ID, 8) + +/* larb2 */ +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) +#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3) +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) +#define M4U_PORT_CAM_IMGO_S MTK_M4U_ID(M4U_LARB2_ID, 5) +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6) +#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7) +#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8) +#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9) +#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10) +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11) +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12) +#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13) +#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14) +#define M4U_PORT_CAM_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15) +#define M4U_PORT_CAM_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16) +#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17) +#define M4U_PORT_CAM_RB MTK_M4U_ID(M4U_LARB2_ID, 18) +#define M4U_PORT_CAM_RP MTK_M4U_ID(M4U_LARB2_ID, 19) +#define M4U_PORT_CAM_WR MTK_M4U_ID(M4U_LARB2_ID, 20) + +/* larb3 */ +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 5) +#define M4U_PORT_REMDC_SDMA MTK_M4U_ID(M4U_LARB3_ID, 6) +#define M4U_PORT_REMDC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 7) +#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) +#define M4U_PORT_JPGENC_SDMA MTK_M4U_ID(M4U_LARB3_ID, 9) +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 10) +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 11) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 12) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 13) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 14) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 15) +#define M4U_PORT_REMDC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 16) +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 17) +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 18) + +/* larb4 */ +#define M4U_PORT_MJC_MV_RD MTK_M4U_ID(M4U_LARB4_ID, 0) +#define M4U_PORT_MJC_MV_WR MTK_M4U_ID(M4U_LARB4_ID, 1) +#define M4U_PORT_MJC_DMA_RD MTK_M4U_ID(M4U_LARB4_ID, 2) +#define M4U_PORT_MJC_DMA_WR MTK_M4U_ID(M4U_LARB4_ID, 3) + +#endif -- 2.35.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: mediatek: Add bindings for MT6795 M4U 2022-06-09 10:39 ` [PATCH v3 1/3] dt-bindings: mediatek: Add bindings for MT6795 M4U AngeloGioacchino Del Regno @ 2022-06-13 5:32 ` Yong Wu 0 siblings, 0 replies; 7+ messages in thread From: Yong Wu @ 2022-06-13 5:32 UTC (permalink / raw) To: AngeloGioacchino Del Regno Cc: joro, will, robh+dt, krzysztof.kozlowski+dt, matthias.bgg, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, konrad.dybcio, marijn.suijten, martin.botka, ~postmarketos/upstreaming, phone-devel, paul.bouchara, Rob Herring On Thu, 2022-06-09 at 12:39 +0200, AngeloGioacchino Del Regno wrote: > Add bindings for the MediaTek Helio X10 (MT6795) IOMMU/M4U. > > Signed-off-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Acked-by: Rob Herring <robh@kernel.org> > --- > .../bindings/iommu/mediatek,iommu.yaml | 4 + > include/dt-bindings/memory/mt6795-larb-port.h | 96 > +++++++++++++++++++ > 2 files changed, 100 insertions(+) > create mode 100644 include/dt-bindings/memory/mt6795-larb-port.h > > diff --git > a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > index d5e3272a54e8..20902c387520 100644 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > @@ -73,6 +73,7 @@ properties: > - mediatek,mt2701-m4u # generation one > - mediatek,mt2712-m4u # generation two > - mediatek,mt6779-m4u # generation two > + - mediatek,mt6795-m4u # generation two > - mediatek,mt8167-m4u # generation two > - mediatek,mt8173-m4u # generation two > - mediatek,mt8183-m4u # generation two > @@ -128,6 +129,7 @@ properties: > dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, > dt-binding/memory/mt2712-larb-port.h for mt2712, > dt-binding/memory/mt6779-larb-port.h for mt6779, > + dt-binding/memory/mt6795-larb-port.h for mt6795, > dt-binding/memory/mt8167-larb-port.h for mt8167, > dt-binding/memory/mt8173-larb-port.h for mt8173, > dt-binding/memory/mt8183-larb-port.h for mt8183, > @@ -152,6 +154,7 @@ allOf: > enum: > - mediatek,mt2701-m4u > - mediatek,mt2712-m4u > + - mediatek,mt6795-m4u > - mediatek,mt8173-m4u > - mediatek,mt8186-iommu-mm > - mediatek,mt8192-m4u > @@ -181,6 +184,7 @@ allOf: > contains: > enum: > - mediatek,mt2712-m4u > + - mediatek,mt6795-m4u > - mediatek,mt8173-m4u > > then: > diff --git a/include/dt-bindings/memory/mt6795-larb-port.h > b/include/dt-bindings/memory/mt6795-larb-port.h > new file mode 100644 > index 000000000000..223aca8fd350 > --- /dev/null > +++ b/include/dt-bindings/memory/mt6795-larb-port.h > @@ -0,0 +1,96 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2022 Collabora Ltd. > + * Author: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > + */ > + > +#ifndef _DT_BINDINGS_MEMORY_MT6795_LARB_PORT_H_ > +#define _DT_BINDINGS_MEMORY_MT6795_LARB_PORT_H_ > + > +#include <dt-bindings/memory/mtk-memory-port.h> > + > +#define M4U_LARB0_ID 0 > +#define M4U_LARB1_ID 1 > +#define M4U_LARB2_ID 2 > +#define M4U_LARB3_ID 3 > +#define M4U_LARB4_ID 4 > +#define M4U_LARB5_ID 5 Just a nitpick: M4U_LARB5_ID is not used, then remove this. > + > +/* larb0 */ > +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) > +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) > +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 2) > +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) > +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) > +#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 5) > +#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB0_ID, 6) > +#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 7) > +#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 8) > +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 9) > +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 10) > +#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 11) > +#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 12) > +#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 13) > + > +/* larb1 */ > +#define M4U_PORT_VDEC_MC MTK_M4U_ID(M4U_LARB1_ID, 0) > +#define M4U_PORT_VDEC_PP MTK_M4U_ID(M4U_LARB1_ID, 1) > +#define M4U_PORT_VDEC_UFO MTK_M4U_ID(M4U_LARB1_ID, 2) > +#define M4U_PORT_VDEC_VLD MTK_M4U_ID(M4U_LARB1_ID, 3) > +#define M4U_PORT_VDEC_VLD2 MTK_M4U_ID(M4U_LARB1_ID, 4) > +#define M4U_PORT_VDEC_AVC_MV MTK_M4U_ID(M4U_LARB1_ID, 5) > +#define M4U_PORT_VDEC_PRED_RD MTK_M4U_ID(M4U_LARB1_ID > , 6) > +#define M4U_PORT_VDEC_PRED_WR MTK_M4U_ID(M4U_LARB1_ID > , 7) > +#define M4U_PORT_VDEC_PPWRAP MTK_M4U_ID(M4U_LARB1_ID, 8) > + > +/* larb2 */ > +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) > +#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) > +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) > +#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3) > +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) > +#define M4U_PORT_CAM_IMGO_S MTK_M4U_ID(M4U_LARB2_ID, 5) > +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6) > +#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7) > +#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8) > +#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9) > +#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10) > +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11) > +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12) > +#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13) > +#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14) > +#define M4U_PORT_CAM_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15) > +#define M4U_PORT_CAM_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16) > +#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17) > +#define M4U_PORT_CAM_RB MTK_M4U_ID(M4U_LARB2_ID > , 18) > +#define M4U_PORT_CAM_RP MTK_M4U_ID(M4U_LARB2_ID > , 19) > +#define M4U_PORT_CAM_WR MTK_M4U_ID(M4U_LARB2_ID > , 20) > + > +/* larb3 */ > +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) > +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) > +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) > +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID > , 3) > +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID > , 4) > +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID > , 5) > +#define M4U_PORT_REMDC_SDMA MTK_M4U_ID(M4U_LARB3_ID, 6) > +#define M4U_PORT_REMDC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 7) > +#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) > +#define M4U_PORT_JPGENC_SDMA MTK_M4U_ID(M4U_LARB3_ID, 9) > +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 10) > +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID > , 11) > +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID > , 12) > +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 13) > +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID > , 14) > +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 15) > +#define M4U_PORT_REMDC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 16) > +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID > , 17) > +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID > , 18) > + > +/* larb4 */ > +#define M4U_PORT_MJC_MV_RD MTK_M4U_ID(M4U_LARB4_ID, 0) > +#define M4U_PORT_MJC_MV_WR MTK_M4U_ID(M4U_LARB4_ID, 1) > +#define M4U_PORT_MJC_DMA_RD MTK_M4U_ID(M4U_LARB4_ID, 2) > +#define M4U_PORT_MJC_DMA_WR MTK_M4U_ID(M4U_LARB4_ID, 3) > + > +#endif ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 2/3] iommu: mtk_iommu: Introduce new flag TF_PORT_TO_ADDR_MT8173 2022-06-09 10:39 [PATCH v3 0/3] MediaTek Helio X10 MT6795 - M4U/IOMMU Support AngeloGioacchino Del Regno 2022-06-09 10:39 ` [PATCH v3 1/3] dt-bindings: mediatek: Add bindings for MT6795 M4U AngeloGioacchino Del Regno @ 2022-06-09 10:40 ` AngeloGioacchino Del Regno 2022-06-13 5:32 ` Yong Wu 2022-06-09 10:40 ` [PATCH v3 3/3] iommu: mtk_iommu: Add support for MT6795 Helio X10 M4Us AngeloGioacchino Del Regno 2 siblings, 1 reply; 7+ messages in thread From: AngeloGioacchino Del Regno @ 2022-06-09 10:40 UTC (permalink / raw) To: yong.wu Cc: joro, will, robh+dt, krzysztof.kozlowski+dt, matthias.bgg, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, konrad.dybcio, marijn.suijten, martin.botka, ~postmarketos/upstreaming, phone-devel, paul.bouchara, AngeloGioacchino Del Regno In preparation for adding support for MT6795, add a new flag named TF_PORT_TO_ADDR_MT8173 and use that instead of checking for m4u_plat type in mtk_iommu_hw_init() to avoid seeing a long list of m4u_plat checks there in the future. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/iommu/mtk_iommu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 0ea0848581e9..8611cf8e4bd5 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -140,6 +140,7 @@ #define IFA_IOMMU_PCIE_SUPPORT BIT(16) /* IOMMU I/O (r/w) is enabled using PERICFG_IOMMU_1 register */ #define HAS_PERI_IOMMU1_REG BIT(17) +#define TF_PORT_TO_ADDR_MT8173 BIT(18) #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) == (_x)) @@ -960,7 +961,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int ban * Global control settings are in bank0. May re-init these global registers * since no sure if there is bank0 consumers. */ - if (data->plat_data->m4u_plat == M4U_MT8173) { + if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { regval = F_MMU_PREFETCH_RT_REPLACE_MOD | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; } else { @@ -1437,7 +1438,8 @@ static const struct mtk_iommu_plat_data mt8167_data = { static const struct mtk_iommu_plat_data mt8173_data = { .m4u_plat = M4U_MT8173, .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | - HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | + TF_PORT_TO_ADDR_MT8173, .inv_sel_reg = REG_MMU_INV_SEL_GEN1, .banks_num = 1, .banks_enable = {true}, -- 2.35.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 2/3] iommu: mtk_iommu: Introduce new flag TF_PORT_TO_ADDR_MT8173 2022-06-09 10:40 ` [PATCH v3 2/3] iommu: mtk_iommu: Introduce new flag TF_PORT_TO_ADDR_MT8173 AngeloGioacchino Del Regno @ 2022-06-13 5:32 ` Yong Wu 0 siblings, 0 replies; 7+ messages in thread From: Yong Wu @ 2022-06-13 5:32 UTC (permalink / raw) To: AngeloGioacchino Del Regno Cc: joro, will, robh+dt, krzysztof.kozlowski+dt, matthias.bgg, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, konrad.dybcio, marijn.suijten, martin.botka, ~postmarketos/upstreaming, phone-devel, paul.bouchara On Thu, 2022-06-09 at 12:40 +0200, AngeloGioacchino Del Regno wrote: > In preparation for adding support for MT6795, add a new flag named > TF_PORT_TO_ADDR_MT8173 and use that instead of checking for m4u_plat > type in mtk_iommu_hw_init() to avoid seeing a long list of m4u_plat > checks there in the future. > > Signed-off-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> Retitle to: iommu/mediatek: Xxx, then Reviewed-by: Yong Wu <yong.wu@mediatek.com> > --- > drivers/iommu/mtk_iommu.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 0ea0848581e9..8611cf8e4bd5 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -140,6 +140,7 @@ > #define IFA_IOMMU_PCIE_SUPPORT BIT(16) > /* IOMMU I/O (r/w) is enabled using PERICFG_IOMMU_1 register */ > #define HAS_PERI_IOMMU1_REG BIT(17) > +#define TF_PORT_TO_ADDR_MT8173 BIT(18) > > #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ > ((((pdata)->flags) & (mask)) == (_x)) > @@ -960,7 +961,7 @@ static int mtk_iommu_hw_init(const struct > mtk_iommu_data *data, unsigned int ban > * Global control settings are in bank0. May re-init these > global registers > * since no sure if there is bank0 consumers. > */ > - if (data->plat_data->m4u_plat == M4U_MT8173) { > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, > TF_PORT_TO_ADDR_MT8173)) { > regval = F_MMU_PREFETCH_RT_REPLACE_MOD | > F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; > } else { > @@ -1437,7 +1438,8 @@ static const struct mtk_iommu_plat_data > mt8167_data = { > static const struct mtk_iommu_plat_data mt8173_data = { > .m4u_plat = M4U_MT8173, > .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | > - HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, > + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | > + TF_PORT_TO_ADDR_MT8173, > .inv_sel_reg = REG_MMU_INV_SEL_GEN1, > .banks_num = 1, > .banks_enable = {true}, ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 3/3] iommu: mtk_iommu: Add support for MT6795 Helio X10 M4Us 2022-06-09 10:39 [PATCH v3 0/3] MediaTek Helio X10 MT6795 - M4U/IOMMU Support AngeloGioacchino Del Regno 2022-06-09 10:39 ` [PATCH v3 1/3] dt-bindings: mediatek: Add bindings for MT6795 M4U AngeloGioacchino Del Regno 2022-06-09 10:40 ` [PATCH v3 2/3] iommu: mtk_iommu: Introduce new flag TF_PORT_TO_ADDR_MT8173 AngeloGioacchino Del Regno @ 2022-06-09 10:40 ` AngeloGioacchino Del Regno 2022-06-13 5:32 ` Yong Wu 2 siblings, 1 reply; 7+ messages in thread From: AngeloGioacchino Del Regno @ 2022-06-09 10:40 UTC (permalink / raw) To: yong.wu Cc: joro, will, robh+dt, krzysztof.kozlowski+dt, matthias.bgg, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, konrad.dybcio, marijn.suijten, martin.botka, ~postmarketos/upstreaming, phone-devel, paul.bouchara, AngeloGioacchino Del Regno Add support for the M4Us found in the MT6795 Helio X10 SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/iommu/mtk_iommu.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 8611cf8e4bd5..beca1c5a6c10 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -160,6 +160,7 @@ enum mtk_iommu_plat { M4U_MT2712, M4U_MT6779, + M4U_MT6795, M4U_MT8167, M4U_MT8173, M4U_MT8183, @@ -1424,6 +1425,19 @@ static const struct mtk_iommu_plat_data mt6779_data = { .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, }; +static const struct mtk_iommu_plat_data mt6795_data = { + .m4u_plat = M4U_MT6795, + .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | + TF_PORT_TO_ADDR_MT8173, + .inv_sel_reg = REG_MMU_INV_SEL_GEN1, + .banks_num = 1, + .banks_enable = {true}, + .iova_region = single_domain, + .iova_region_nr = ARRAY_SIZE(single_domain), + .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */ +}; + static const struct mtk_iommu_plat_data mt8167_data = { .m4u_plat = M4U_MT8167, .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, @@ -1536,6 +1550,7 @@ static const struct mtk_iommu_plat_data mt8195_data_vpp = { static const struct of_device_id mtk_iommu_of_ids[] = { { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, + { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data}, { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, -- 2.35.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 3/3] iommu: mtk_iommu: Add support for MT6795 Helio X10 M4Us 2022-06-09 10:40 ` [PATCH v3 3/3] iommu: mtk_iommu: Add support for MT6795 Helio X10 M4Us AngeloGioacchino Del Regno @ 2022-06-13 5:32 ` Yong Wu 0 siblings, 0 replies; 7+ messages in thread From: Yong Wu @ 2022-06-13 5:32 UTC (permalink / raw) To: AngeloGioacchino Del Regno Cc: joro, will, robh+dt, krzysztof.kozlowski+dt, matthias.bgg, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, konrad.dybcio, marijn.suijten, martin.botka, ~postmarketos/upstreaming, phone-devel, paul.bouchara On Thu, 2022-06-09 at 12:40 +0200, AngeloGioacchino Del Regno wrote: > Add support for the M4Us found in the MT6795 Helio X10 SoC. > > Signed-off-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> Retitle to: iommu/mediatek: Xxx, then Reviewed-by: Yong Wu <yong.wu@mediatek.com> > --- > drivers/iommu/mtk_iommu.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 8611cf8e4bd5..beca1c5a6c10 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -160,6 +160,7 @@ > enum mtk_iommu_plat { > M4U_MT2712, > M4U_MT6779, > + M4U_MT6795, > M4U_MT8167, > M4U_MT8173, > M4U_MT8183, > @@ -1424,6 +1425,19 @@ static const struct mtk_iommu_plat_data > mt6779_data = { > .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, > }; > > +static const struct mtk_iommu_plat_data mt6795_data = { > + .m4u_plat = M4U_MT6795, > + .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | > + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | > + TF_PORT_TO_ADDR_MT8173, > + .inv_sel_reg = REG_MMU_INV_SEL_GEN1, > + .banks_num = 1, > + .banks_enable = {true}, > + .iova_region = single_domain, > + .iova_region_nr = ARRAY_SIZE(single_domain), > + .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. > */ > +}; > + > static const struct mtk_iommu_plat_data mt8167_data = { > .m4u_plat = M4U_MT8167, > .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | > MTK_IOMMU_TYPE_MM, > @@ -1536,6 +1550,7 @@ static const struct mtk_iommu_plat_data > mt8195_data_vpp = { > static const struct of_device_id mtk_iommu_of_ids[] = { > { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, > { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, > + { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data}, > { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, > { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, > { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-06-13 5:33 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-06-09 10:39 [PATCH v3 0/3] MediaTek Helio X10 MT6795 - M4U/IOMMU Support AngeloGioacchino Del Regno 2022-06-09 10:39 ` [PATCH v3 1/3] dt-bindings: mediatek: Add bindings for MT6795 M4U AngeloGioacchino Del Regno 2022-06-13 5:32 ` Yong Wu 2022-06-09 10:40 ` [PATCH v3 2/3] iommu: mtk_iommu: Introduce new flag TF_PORT_TO_ADDR_MT8173 AngeloGioacchino Del Regno 2022-06-13 5:32 ` Yong Wu 2022-06-09 10:40 ` [PATCH v3 3/3] iommu: mtk_iommu: Add support for MT6795 Helio X10 M4Us AngeloGioacchino Del Regno 2022-06-13 5:32 ` Yong Wu
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