Re: [PATCH v4 09/13] ARM: dts: lan966x: add MIIM nodes

[<Claudiu.Beznea@microchip.com>]

On 03.05.2022 01:41, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Add the MDIO controller nodes. The integrated PHYs are connected to the
> second controller. This controller also takes care of the resets of the
> integrated PHYs, thus it has two memory regions. The first controller
> is routed to the external MDIO/MDC pins.
> 
> By default, they are disabled.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
>  arch/arm/boot/dts/lan966x.dtsi | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 64290fb43926..0442735910da 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -418,6 +418,37 @@ gpio: pinctrl@e2004064 {
>                         #interrupt-cells = <2>;
>                 };
> 
> +               mdio0: mdio@e2004118 {
> +                       compatible = "microchip,lan966x-miim";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0xe2004118 0x24>;
> +                       clocks = <&sys_clk>;
> +                       status = "disabled";
> +               };
> +
> +               mdio1: mdio@e200413c {
> +                       compatible = "microchip,lan966x-miim";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0xe200413c 0x24>,
> +                             <0xe2010020 0x4>;
> +                       clocks = <&sys_clk>;
> +                       status = "disabled";
> +
> +                       phy0: ethernet-phy@1 {
> +                               reg = <1>;
> +                               interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +                               status = "disabled";
> +                       };
> +
> +                       phy1: ethernet-phy@2 {
> +                               reg = <2>;
> +                               interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +                               status = "disabled";
> +                       };
> +               };
> +
>                 sgpio: gpio@e2004190 {
>                         compatible = "microchip,sparx5-sgpio";
>                         reg = <0xe2004190 0x118>;
> --
> 2.30.2
>