[PATCH] dt-bindings: misc: add schema for xlnx,axi-fifo-mm-s

[PATCH] dt-bindings: misc: add schema for xlnx,axi-fifo-mm-s

[Lucas Faria Mendes]

Add a proper YAML devicetree binding schema for the Xilinx AXI-Stream
FIFO IP core, documenting the three supported compatible strings:
xlnx,axi-fifo-mm-s-4.1, xlnx,axi-fifo-mm-s-4.2, and
xlnx,axi-fifo-mm-s-4.3.

This resolves the checkpatch warnings about undocumented DT compatible
strings.

Signed-off-by: Lucas Faria Mendes <lucas.fariamo08@gmail.com>
---
 .../bindings/misc/xlnx,axi-fifo-mm-s.yaml     | 102 ++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml

diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
new file mode 100644
index 000000000000..dbb5425e39d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx AXI-Stream FIFO IP core
+
+maintainers:
+  - Jacob Feder <jacobsfeder@gmail.com>
+
+description: |
+  The Xilinx AXI-Stream FIFO IP core has read and write AXI-Stream FIFOs,
+  the contents of which can be accessed from the AXI4 memory-mapped interface.
+  This is useful for transferring data from a processor into the FPGA fabric.
+  The driver creates a character device that can be read/written to with
+  standard open/read/write/close.
+
+  See Xilinx PG080 document for IP details.
+
+  Currently supports only store-forward mode with a 32-bit AXI4-Lite
+  interface.
+
+properties:
+  compatible:
+    enum:
+      - xlnx,axi-fifo-mm-s-4.1
+      - xlnx,axi-fifo-mm-s-4.2
+      - xlnx,axi-fifo-mm-s-4.3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    items:
+      - const: interrupt
+
+  xlnx,axi-str-rxd-tdata-width:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    const: 32
+    description:
+      AXI-Stream RX data width in bits. Only 32-bit is supported.
+
+  xlnx,axi-str-txd-tdata-width:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    const: 32
+    description:
+      AXI-Stream TX data width in bits. Only 32-bit is supported.
+
+  xlnx,rx-fifo-depth:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Depth of RX FIFO in words.
+
+  xlnx,tx-fifo-depth:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Depth of TX FIFO in words.
+
+  xlnx,use-rx-data:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1]
+    description:
+      1 if RX FIFO is enabled, 0 otherwise.
+
+  xlnx,use-tx-data:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1]
+    description:
+      1 if TX FIFO is enabled, 0 otherwise.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - xlnx,axi-str-rxd-tdata-width
+  - xlnx,axi-str-txd-tdata-width
+  - xlnx,rx-fifo-depth
+  - xlnx,tx-fifo-depth
+  - xlnx,use-rx-data
+  - xlnx,use-tx-data
+
+additionalProperties: false
+
+examples:
+  - |
+    axi_fifo_mm_s@43c00000 {
+        compatible = "xlnx,axi-fifo-mm-s-4.1";
+        interrupt-names = "interrupt";
+        interrupt-parent = <&intc>;
+        interrupts = <0 29 4>;
+        reg = <0x43c00000 0x10000>;
+        xlnx,axi-str-rxd-tdata-width = <0x20>;
+        xlnx,axi-str-txd-tdata-width = <0x20>;
+        xlnx,rx-fifo-depth = <0x200>;
+        xlnx,tx-fifo-depth = <0x8000>;
+        xlnx,use-rx-data = <0x0>;
+        xlnx,use-tx-data = <0x1>;
+    };
-- 
2.53.0

Re: [PATCH] dt-bindings: misc: add schema for xlnx,axi-fifo-mm-s

[Conor Dooley]

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On Fri, Feb 27, 2026 at 02:30:44PM -0300, Lucas Faria Mendes wrote:
> Add a proper YAML devicetree binding schema for the Xilinx AXI-Stream
> FIFO IP core, documenting the three supported compatible strings:
> xlnx,axi-fifo-mm-s-4.1, xlnx,axi-fifo-mm-s-4.2, and
> xlnx,axi-fifo-mm-s-4.3.
> 
> This resolves the checkpatch warnings about undocumented DT compatible
> strings.
> 
> Signed-off-by: Lucas Faria Mendes <lucas.fariamo08@gmail.com>
> ---
>  .../bindings/misc/xlnx,axi-fifo-mm-s.yaml     | 102 ++++++++++++++++++
>  1 file changed, 102 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> 
> diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> new file mode 100644
> index 000000000000..dbb5425e39d6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> @@ -0,0 +1,102 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx AXI-Stream FIFO IP core
> +
> +maintainers:
> +  - Jacob Feder <jacobsfeder@gmail.com>
> +
> +description: |
> +  The Xilinx AXI-Stream FIFO IP core has read and write AXI-Stream FIFOs,
> +  the contents of which can be accessed from the AXI4 memory-mapped interface.
> +  This is useful for transferring data from a processor into the FPGA fabric.

Isn't this basically a dma controller?

> +  The driver creates a character device that can be read/written to with
> +  standard open/read/write/close.

This has nothing to do with the binding. I went looking for the driver
and realised it is in staging, and there's a text binding in staging
which this patch should be deleting!
Are you trying to get this out of staging? I don't know how much value
there is in trying to convert the binding if the driver isn't going to
be moved out.

> +
> +  See Xilinx PG080 document for IP details.
> +
> +  Currently supports only store-forward mode with a 32-bit AXI4-Lite
> +  interface.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - xlnx,axi-fifo-mm-s-4.1
> +      - xlnx,axi-fifo-mm-s-4.2
> +      - xlnx,axi-fifo-mm-s-4.3

I find it kinda suspect that minor version changes cause incompatible
changes in the programming model.

> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-names:
> +    items:
> +      - const: interrupt
> +
> +  xlnx,axi-str-rxd-tdata-width:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    const: 32
> +    description:
> +      AXI-Stream RX data width in bits. Only 32-bit is supported.
> +
> +  xlnx,axi-str-txd-tdata-width:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    const: 32
> +    description:
> +      AXI-Stream TX data width in bits. Only 32-bit is supported.

Why do these need properties if they are only 32-bit always? Is that
limitation on the driver? If so, the binding should permit what the
hardware can do.

> +
> +  xlnx,rx-fifo-depth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Depth of RX FIFO in words.
> +
> +  xlnx,tx-fifo-depth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Depth of TX FIFO in words.
> +
> +  xlnx,use-rx-data:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1]
> +    description:
> +      1 if RX FIFO is enabled, 0 otherwise.

These two should be booleans.

> +
> +  xlnx,use-tx-data:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1]
> +    description:
> +      1 if TX FIFO is enabled, 0 otherwise.
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - xlnx,axi-str-rxd-tdata-width
> +  - xlnx,axi-str-txd-tdata-width
> +  - xlnx,rx-fifo-depth
> +  - xlnx,tx-fifo-depth
> +  - xlnx,use-rx-data
> +  - xlnx,use-tx-data

And if the properties become boolean, they aren't required any more.

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    axi_fifo_mm_s@43c00000 {

I think this should be "dma-controller".

> +        compatible = "xlnx,axi-fifo-mm-s-4.1";
> +        interrupt-names = "interrupt";
> +        interrupt-parent = <&intc>;
> +        interrupts = <0 29 4>;
> +        reg = <0x43c00000 0x10000>;

reg should be after properties.

pw-bot: changes-requested

Thanks,
Conor.

> +        xlnx,axi-str-rxd-tdata-width = <0x20>;
> +        xlnx,axi-str-txd-tdata-width = <0x20>;
> +        xlnx,rx-fifo-depth = <0x200>;
> +        xlnx,tx-fifo-depth = <0x8000>;
> +        xlnx,use-rx-data = <0x0>;
> +        xlnx,use-tx-data = <0x1>;
> +    };
> -- 
> 2.53.0
> 

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[PATCH v2 0/3] staging: axis-fifo: convert bindings to YAML and fix style

[Lucas Faria Mendes]

This series converts the Xilinx AXI-Stream FIFO bindings from legacy
text format to a modern YAML json-schema. Additionally, it fixes
coding style issues in the driver and updates it to match the new
binding's boolean properties.

Changes since v1:
- Converted xlnx,use-rx-data and xlnx,use-tx-data to booleans in the
  YAML schema and the driver code.
- Removed the rigid 32-bit data width check in the driver to better
  align with hardware description principles.
- Renamed the example node to "dma-controller" and reordered the 
  'reg' property.
- Deleted the legacy text binding file that was replaced by the YAML 
  schema.
- Fixed a checkpatch.pl alignment warning.

Lucas Faria Mendes (3):
  staging: axis-fifo: fix alignment to match open parenthesis
  dt-bindings: misc: xlnx,axi-fifo-mm-s: convert to json-schema
  staging: axis-fifo: fix alignment and handle boolean properties

 .../bindings/misc/xlnx,axi-fifo-mm-s.yaml     | 91 ++++++++++++++++++
 drivers/staging/axis-fifo/axis-fifo.c         | 58 +++--------
 drivers/staging/axis-fifo/axis-fifo.txt       | 96 -------------------
 3 files changed, 106 insertions(+), 139 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
 delete mode 100644 drivers/staging/axis-fifo/axis-fifo.txt

-- 
2.53.0

[PATCH v2 1/3] staging: axis-fifo: fix alignment to match open parenthesis

[Lucas Faria Mendes]

Fix checkpatch CHECK for alignment in the wait_event_interruptible()
call. Align the continuation line to match the open parenthesis as
required by the kernel coding style.

Signed-off-by: Lucas Faria Mendes <lucas.fariamo08@gmail.com>
---
 drivers/staging/axis-fifo/axis-fifo.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-fifo/axis-fifo.c
index aa90b27197cf..c64a7249feca 100644
--- a/drivers/staging/axis-fifo/axis-fifo.c
+++ b/drivers/staging/axis-fifo/axis-fifo.c
@@ -246,7 +246,8 @@ static ssize_t axis_fifo_write(struct file *f, const char __user *buf,
 		mutex_lock(&fifo->write_lock);
 
 		ret = wait_event_interruptible(fifo->write_queue,
-			ioread32(fifo->base_addr + XLLF_TDFV_OFFSET) >= words_to_write);
+					       ioread32(fifo->base_addr + XLLF_TDFV_OFFSET)
+					       >= words_to_write);
 		if (ret)
 			goto end_unlock;
 	}
-- 
2.53.0

[PATCH v2 2/3] dt-bindings: misc: xlnx,axi-fifo-mm-s: convert to json-schema

[Lucas Faria Mendes]

---
 .../bindings/misc/xlnx,axi-fifo-mm-s.yaml     | 91 ++++++++++++++++++
 drivers/staging/axis-fifo/axis-fifo.txt       | 96 -------------------
 2 files changed, 91 insertions(+), 96 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
 delete mode 100644 drivers/staging/axis-fifo/axis-fifo.txt

diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
new file mode 100644
index 000000000000..967d681f3980
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx AXI-Stream FIFO IP core
+
+maintainers:
+  - Jacob Feder <jacobsfeder@gmail.com>
+
+description: |
+  The Xilinx AXI-Stream FIFO IP core has read and write AXI-Stream FIFOs,
+  the contents of which can be accessed from the AXI4 memory-mapped interface.
+  This is useful for transferring data from a processor into the FPGA fabric.
+
+  See Xilinx PG080 document for IP details.
+
+  Currently supports only store-forward mode with a 32-bit AXI4-Lite
+  interface.
+
+properties:
+  compatible:
+    enum:
+      - xlnx,axi-fifo-mm-s-4.1
+      - xlnx,axi-fifo-mm-s-4.2
+      - xlnx,axi-fifo-mm-s-4.3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    items:
+      - const: interrupt
+
+  xlnx,axi-str-rxd-tdata-width:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      AXI-Stream RX data width in bits. Only 32-bit is supported.
+
+  xlnx,axi-str-txd-tdata-width:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      AXI-Stream TX data width in bits. Only 32-bit is supported.
+
+  xlnx,rx-fifo-depth:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Depth of RX FIFO in words.
+
+  xlnx,tx-fifo-depth:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Depth of TX FIFO in words.
+
+  xlnx,use-rx-data:
+    type: boolean
+    description: RX FIFO is enabled.
+
+  xlnx,use-tx-data:
+    type: boolean
+    description: TX FIFO is enabled.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - xlnx,axi-str-rxd-tdata-width
+  - xlnx,axi-str-txd-tdata-width
+  - xlnx,rx-fifo-depth
+  - xlnx,tx-fifo-depth
+
+additionalProperties: false
+
+examples:
+  - |
+    dma-controller@43c00000 {
+        compatible = "xlnx,axi-fifo-mm-s-4.1";
+        reg = <0x43c00000 0x10000>;
+        interrupt-names = "interrupt";
+        interrupt-parent = <&intc>;
+        interrupts = <0 29 4>;
+        xlnx,axi-str-rxd-tdata-width = <32>;
+        xlnx,axi-str-txd-tdata-width = <32>;
+        xlnx,rx-fifo-depth = <512>;
+        xlnx,tx-fifo-depth = <32768>;
+        xlnx,use-tx-data;
+    };
diff --git a/drivers/staging/axis-fifo/axis-fifo.txt b/drivers/staging/axis-fifo/axis-fifo.txt
deleted file mode 100644
index 413b81a53202..000000000000
--- a/drivers/staging/axis-fifo/axis-fifo.txt
+++ /dev/null
@@ -1,96 +0,0 @@
-Xilinx AXI-Stream FIFO v4.1 IP core
-
-This IP core has read and write AXI-Stream FIFOs, the contents of which can
-be accessed from the AXI4 memory-mapped interface. This is useful for
-transferring data from a processor into the FPGA fabric. The driver creates
-a character device that can be read/written to with standard
-open/read/write/close.
-
-See Xilinx PG080 document for IP details.
-
-Currently supports only store-forward mode with a 32-bit
-AXI4-Lite interface. DOES NOT support:
-	- cut-through mode
-	- AXI4 (non-lite)
-
-Required properties:
-- compatible: Should be one of:
-    "xlnx,axi-fifo-mm-s-4.1"
-    "xlnx,axi-fifo-mm-s-4.2"
-    "xlnx,axi-fifo-mm-s-4.3"
-- interrupt-names: Should be "interrupt"
-- interrupt-parent: Should be <&intc>
-- interrupts: Should contain interrupts lines.
-- reg: Should contain registers location and length.
-- xlnx,axi-str-rxd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA"
-- xlnx,axi-str-rxd-tdata-width: Should be <0x20>
-- xlnx,axi-str-txc-protocol: Should be "XIL_AXI_STREAM_ETH_CTRL"
-- xlnx,axi-str-txc-tdata-width: Should be <0x20>
-- xlnx,axi-str-txd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA"
-- xlnx,axi-str-txd-tdata-width: Should be <0x20>
-- xlnx,axis-tdest-width: AXI-Stream TDEST width (ignored by the driver)
-- xlnx,axis-tid-width: AXI-Stream TID width (ignored by the driver)
-- xlnx,axis-tuser-width: AXI-Stream TUSER width (ignored by the driver)
-- xlnx,data-interface-type: Should be <0x0> (ignored by the driver)
-- xlnx,has-axis-tdest: Should be <0x0> (this feature isn't supported)
-- xlnx,has-axis-tid: Should be <0x0> (this feature isn't supported)
-- xlnx,has-axis-tkeep: Should be <0x0> (this feature isn't supported)
-- xlnx,has-axis-tstrb: Should be <0x0> (this feature isn't supported)
-- xlnx,has-axis-tuser: Should be <0x0> (this feature isn't supported)
-- xlnx,rx-fifo-depth: Depth of RX FIFO in words
-- xlnx,rx-fifo-pe-threshold: RX programmable empty interrupt threshold
-	(ignored by the driver)
-- xlnx,rx-fifo-pf-threshold: RX programmable full interrupt threshold
-	(ignored by the driver)
-- xlnx,s-axi-id-width: Should be <0x4> (ignored by the driver)
-- xlnx,s-axi4-data-width: Should be <0x20> (ignored by the driver)
-- xlnx,select-xpm: Should be <0x0> (ignored by the driver)
-- xlnx,tx-fifo-depth: Depth of TX FIFO in words
-- xlnx,tx-fifo-pe-threshold: TX programmable empty interrupt threshold
-	(ignored by the driver)
-- xlnx,tx-fifo-pf-threshold: TX programmable full interrupt threshold
-	(ignored by the driver)
-- xlnx,use-rx-cut-through: Should be <0x0> (this feature isn't supported)
-- xlnx,use-rx-data: <0x1> if RX FIFO is enabled, <0x0> otherwise
-- xlnx,use-tx-ctrl: Should be <0x0> (this feature isn't supported)
-- xlnx,use-tx-cut-through: Should be <0x0> (this feature isn't supported)
-- xlnx,use-tx-data: <0x1> if TX FIFO is enabled, <0x0> otherwise
-
-Example:
-
-axi_fifo_mm_s_0: axi_fifo_mm_s@43c00000 {
-	compatible = "xlnx,axi-fifo-mm-s-4.1";
-	interrupt-names = "interrupt";
-	interrupt-parent = <&intc>;
-	interrupts = <0 29 4>;
-	reg = <0x43c00000 0x10000>;
-	xlnx,axi-str-rxd-protocol = "XIL_AXI_STREAM_ETH_DATA";
-	xlnx,axi-str-rxd-tdata-width = <0x20>;
-	xlnx,axi-str-txc-protocol = "XIL_AXI_STREAM_ETH_CTRL";
-	xlnx,axi-str-txc-tdata-width = <0x20>;
-	xlnx,axi-str-txd-protocol = "XIL_AXI_STREAM_ETH_DATA";
-	xlnx,axi-str-txd-tdata-width = <0x20>;
-	xlnx,axis-tdest-width = <0x4>;
-	xlnx,axis-tid-width = <0x4>;
-	xlnx,axis-tuser-width = <0x4>;
-	xlnx,data-interface-type = <0x0>;
-	xlnx,has-axis-tdest = <0x0>;
-	xlnx,has-axis-tid = <0x0>;
-	xlnx,has-axis-tkeep = <0x0>;
-	xlnx,has-axis-tstrb = <0x0>;
-	xlnx,has-axis-tuser = <0x0>;
-	xlnx,rx-fifo-depth = <0x200>;
-	xlnx,rx-fifo-pe-threshold = <0x2>;
-	xlnx,rx-fifo-pf-threshold = <0x1fb>;
-	xlnx,s-axi-id-width = <0x4>;
-	xlnx,s-axi4-data-width = <0x20>;
-	xlnx,select-xpm = <0x0>;
-	xlnx,tx-fifo-depth = <0x8000>;
-	xlnx,tx-fifo-pe-threshold = <0x200>;
-	xlnx,tx-fifo-pf-threshold = <0x7ffb>;
-	xlnx,use-rx-cut-through = <0x0>;
-	xlnx,use-rx-data = <0x0>;
-	xlnx,use-tx-ctrl = <0x0>;
-	xlnx,use-tx-cut-through = <0x0>;
-	xlnx,use-tx-data = <0x1>;
-};
-- 
2.53.0

Re: [PATCH v2 2/3] dt-bindings: misc: xlnx,axi-fifo-mm-s: convert to json-schema

[Conor Dooley]

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On Fri, Feb 27, 2026 at 03:10:44PM -0300, Lucas Faria Mendes wrote:
> ---

You've resent here far too quickly chief, without a commit message and
with half of my comments unimplemented or not responded to.

Please take the time to read through my earlier review and complete the
discussion there before sending a new version.

Additionally, please do not send new versions as a reply to an old one.

Cheers,
Conor.

>  .../bindings/misc/xlnx,axi-fifo-mm-s.yaml     | 91 ++++++++++++++++++
>  drivers/staging/axis-fifo/axis-fifo.txt       | 96 -------------------
>  2 files changed, 91 insertions(+), 96 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
>  delete mode 100644 drivers/staging/axis-fifo/axis-fifo.txt
> 
> diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> new file mode 100644
> index 000000000000..967d681f3980
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
> @@ -0,0 +1,91 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx AXI-Stream FIFO IP core
> +
> +maintainers:
> +  - Jacob Feder <jacobsfeder@gmail.com>
> +
> +description: |
> +  The Xilinx AXI-Stream FIFO IP core has read and write AXI-Stream FIFOs,
> +  the contents of which can be accessed from the AXI4 memory-mapped interface.
> +  This is useful for transferring data from a processor into the FPGA fabric.
> +
> +  See Xilinx PG080 document for IP details.
> +
> +  Currently supports only store-forward mode with a 32-bit AXI4-Lite
> +  interface.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - xlnx,axi-fifo-mm-s-4.1
> +      - xlnx,axi-fifo-mm-s-4.2
> +      - xlnx,axi-fifo-mm-s-4.3
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-names:
> +    items:
> +      - const: interrupt
> +
> +  xlnx,axi-str-rxd-tdata-width:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      AXI-Stream RX data width in bits. Only 32-bit is supported.
> +
> +  xlnx,axi-str-txd-tdata-width:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      AXI-Stream TX data width in bits. Only 32-bit is supported.
> +
> +  xlnx,rx-fifo-depth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Depth of RX FIFO in words.
> +
> +  xlnx,tx-fifo-depth:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Depth of TX FIFO in words.
> +
> +  xlnx,use-rx-data:
> +    type: boolean
> +    description: RX FIFO is enabled.
> +
> +  xlnx,use-tx-data:
> +    type: boolean
> +    description: TX FIFO is enabled.
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - xlnx,axi-str-rxd-tdata-width
> +  - xlnx,axi-str-txd-tdata-width
> +  - xlnx,rx-fifo-depth
> +  - xlnx,tx-fifo-depth
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    dma-controller@43c00000 {
> +        compatible = "xlnx,axi-fifo-mm-s-4.1";
> +        reg = <0x43c00000 0x10000>;
> +        interrupt-names = "interrupt";
> +        interrupt-parent = <&intc>;
> +        interrupts = <0 29 4>;
> +        xlnx,axi-str-rxd-tdata-width = <32>;
> +        xlnx,axi-str-txd-tdata-width = <32>;
> +        xlnx,rx-fifo-depth = <512>;
> +        xlnx,tx-fifo-depth = <32768>;
> +        xlnx,use-tx-data;
> +    };
> diff --git a/drivers/staging/axis-fifo/axis-fifo.txt b/drivers/staging/axis-fifo/axis-fifo.txt
> deleted file mode 100644
> index 413b81a53202..000000000000
> --- a/drivers/staging/axis-fifo/axis-fifo.txt
> +++ /dev/null
> @@ -1,96 +0,0 @@
> -Xilinx AXI-Stream FIFO v4.1 IP core
> -
> -This IP core has read and write AXI-Stream FIFOs, the contents of which can
> -be accessed from the AXI4 memory-mapped interface. This is useful for
> -transferring data from a processor into the FPGA fabric. The driver creates
> -a character device that can be read/written to with standard
> -open/read/write/close.
> -
> -See Xilinx PG080 document for IP details.
> -
> -Currently supports only store-forward mode with a 32-bit
> -AXI4-Lite interface. DOES NOT support:
> -	- cut-through mode
> -	- AXI4 (non-lite)
> -
> -Required properties:
> -- compatible: Should be one of:
> -    "xlnx,axi-fifo-mm-s-4.1"
> -    "xlnx,axi-fifo-mm-s-4.2"
> -    "xlnx,axi-fifo-mm-s-4.3"
> -- interrupt-names: Should be "interrupt"
> -- interrupt-parent: Should be <&intc>
> -- interrupts: Should contain interrupts lines.
> -- reg: Should contain registers location and length.
> -- xlnx,axi-str-rxd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA"
> -- xlnx,axi-str-rxd-tdata-width: Should be <0x20>
> -- xlnx,axi-str-txc-protocol: Should be "XIL_AXI_STREAM_ETH_CTRL"
> -- xlnx,axi-str-txc-tdata-width: Should be <0x20>
> -- xlnx,axi-str-txd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA"
> -- xlnx,axi-str-txd-tdata-width: Should be <0x20>
> -- xlnx,axis-tdest-width: AXI-Stream TDEST width (ignored by the driver)
> -- xlnx,axis-tid-width: AXI-Stream TID width (ignored by the driver)
> -- xlnx,axis-tuser-width: AXI-Stream TUSER width (ignored by the driver)
> -- xlnx,data-interface-type: Should be <0x0> (ignored by the driver)
> -- xlnx,has-axis-tdest: Should be <0x0> (this feature isn't supported)
> -- xlnx,has-axis-tid: Should be <0x0> (this feature isn't supported)
> -- xlnx,has-axis-tkeep: Should be <0x0> (this feature isn't supported)
> -- xlnx,has-axis-tstrb: Should be <0x0> (this feature isn't supported)
> -- xlnx,has-axis-tuser: Should be <0x0> (this feature isn't supported)
> -- xlnx,rx-fifo-depth: Depth of RX FIFO in words
> -- xlnx,rx-fifo-pe-threshold: RX programmable empty interrupt threshold
> -	(ignored by the driver)
> -- xlnx,rx-fifo-pf-threshold: RX programmable full interrupt threshold
> -	(ignored by the driver)
> -- xlnx,s-axi-id-width: Should be <0x4> (ignored by the driver)
> -- xlnx,s-axi4-data-width: Should be <0x20> (ignored by the driver)
> -- xlnx,select-xpm: Should be <0x0> (ignored by the driver)
> -- xlnx,tx-fifo-depth: Depth of TX FIFO in words
> -- xlnx,tx-fifo-pe-threshold: TX programmable empty interrupt threshold
> -	(ignored by the driver)
> -- xlnx,tx-fifo-pf-threshold: TX programmable full interrupt threshold
> -	(ignored by the driver)
> -- xlnx,use-rx-cut-through: Should be <0x0> (this feature isn't supported)
> -- xlnx,use-rx-data: <0x1> if RX FIFO is enabled, <0x0> otherwise
> -- xlnx,use-tx-ctrl: Should be <0x0> (this feature isn't supported)
> -- xlnx,use-tx-cut-through: Should be <0x0> (this feature isn't supported)
> -- xlnx,use-tx-data: <0x1> if TX FIFO is enabled, <0x0> otherwise
> -
> -Example:
> -
> -axi_fifo_mm_s_0: axi_fifo_mm_s@43c00000 {
> -	compatible = "xlnx,axi-fifo-mm-s-4.1";
> -	interrupt-names = "interrupt";
> -	interrupt-parent = <&intc>;
> -	interrupts = <0 29 4>;
> -	reg = <0x43c00000 0x10000>;
> -	xlnx,axi-str-rxd-protocol = "XIL_AXI_STREAM_ETH_DATA";
> -	xlnx,axi-str-rxd-tdata-width = <0x20>;
> -	xlnx,axi-str-txc-protocol = "XIL_AXI_STREAM_ETH_CTRL";
> -	xlnx,axi-str-txc-tdata-width = <0x20>;
> -	xlnx,axi-str-txd-protocol = "XIL_AXI_STREAM_ETH_DATA";
> -	xlnx,axi-str-txd-tdata-width = <0x20>;
> -	xlnx,axis-tdest-width = <0x4>;
> -	xlnx,axis-tid-width = <0x4>;
> -	xlnx,axis-tuser-width = <0x4>;
> -	xlnx,data-interface-type = <0x0>;
> -	xlnx,has-axis-tdest = <0x0>;
> -	xlnx,has-axis-tid = <0x0>;
> -	xlnx,has-axis-tkeep = <0x0>;
> -	xlnx,has-axis-tstrb = <0x0>;
> -	xlnx,has-axis-tuser = <0x0>;
> -	xlnx,rx-fifo-depth = <0x200>;
> -	xlnx,rx-fifo-pe-threshold = <0x2>;
> -	xlnx,rx-fifo-pf-threshold = <0x1fb>;
> -	xlnx,s-axi-id-width = <0x4>;
> -	xlnx,s-axi4-data-width = <0x20>;
> -	xlnx,select-xpm = <0x0>;
> -	xlnx,tx-fifo-depth = <0x8000>;
> -	xlnx,tx-fifo-pe-threshold = <0x200>;
> -	xlnx,tx-fifo-pf-threshold = <0x7ffb>;
> -	xlnx,use-rx-cut-through = <0x0>;
> -	xlnx,use-rx-data = <0x0>;
> -	xlnx,use-tx-ctrl = <0x0>;
> -	xlnx,use-tx-cut-through = <0x0>;
> -	xlnx,use-tx-data = <0x1>;
> -};
> -- 
> 2.53.0
> 

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Re: [PATCH v2 2/3] dt-bindings: misc: xlnx,axi-fifo-mm-s: convert to json-schema

[Rob Herring (Arm)]

On Fri, 27 Feb 2026 15:10:44 -0300, Lucas Faria Mendes wrote:
> ---
>  .../bindings/misc/xlnx,axi-fifo-mm-s.yaml     | 91 ++++++++++++++++++
>  drivers/staging/axis-fifo/axis-fifo.txt       | 96 -------------------
>  2 files changed, 91 insertions(+), 96 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
>  delete mode 100644 drivers/staging/axis-fifo/axis-fifo.txt
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.example.dtb: dma-controller@43c00000 (xlnx,axi-fifo-mm-s-4.1): '#dma-cells' is a required property
	from schema $id: http://devicetree.org/schemas/dma/dma-controller.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20260227181051.36207-3-lucas.fariamo08@gmail.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[PATCH v2 3/3] staging: axis-fifo: fix alignment and handle boolean properties

[Lucas Faria Mendes]

Signed-off-by: Lucas Faria Mendes <lucas.fariamo08@gmail.com>
---
 drivers/staging/axis-fifo/axis-fifo.c | 55 +++++++--------------------
 1 file changed, 13 insertions(+), 42 deletions(-)

diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-fifo/axis-fifo.c
index c64a7249feca..4b2cab2f8357 100644
--- a/drivers/staging/axis-fifo/axis-fifo.c
+++ b/drivers/staging/axis-fifo/axis-fifo.c
@@ -387,66 +387,37 @@ static void axis_fifo_debugfs_init(struct axis_fifo *fifo)
 
 static int axis_fifo_parse_dt(struct axis_fifo *fifo)
 {
-	int ret;
-	unsigned int value;
 	struct device_node *node = fifo->dt_device->of_node;
-
-	ret = of_property_read_u32(node, "xlnx,axi-str-rxd-tdata-width",
-				   &value);
+	int ret;
+	
+	ret = of_property_read_u32(node, "xlnx,axi-str-rxd-tdata-width", &ret);
 	if (ret) {
 		dev_err(fifo->dt_device, "missing xlnx,axi-str-rxd-tdata-width property\n");
-		goto end;
-	} else if (value != 32) {
-		dev_err(fifo->dt_device, "xlnx,axi-str-rxd-tdata-width only supports 32 bits\n");
-		ret = -EIO;
-		goto end;
+		return -EINVAL;
 	}
 
-	ret = of_property_read_u32(node, "xlnx,axi-str-txd-tdata-width",
-				   &value);
+	ret = of_property_read_u32(node, "xlnx,axi-str-txd-tdata-width", &ret);
 	if (ret) {
 		dev_err(fifo->dt_device, "missing xlnx,axi-str-txd-tdata-width property\n");
-		goto end;
-	} else if (value != 32) {
-		dev_err(fifo->dt_device, "xlnx,axi-str-txd-tdata-width only supports 32 bits\n");
-		ret = -EIO;
-		goto end;
+		return -EINVAL;
 	}
 
-	ret = of_property_read_u32(node, "xlnx,rx-fifo-depth",
-				   &fifo->rx_fifo_depth);
+	ret = of_property_read_u32(node, "xlnx,rx-fifo-depth", &fifo->rx_fifo_depth);
 	if (ret) {
 		dev_err(fifo->dt_device, "missing xlnx,rx-fifo-depth property\n");
-		ret = -EIO;
-		goto end;
+		return -EINVAL;
 	}
 
-	ret = of_property_read_u32(node, "xlnx,tx-fifo-depth",
-				   &fifo->tx_fifo_depth);
+	ret = of_property_read_u32(node, "xlnx,tx-fifo-depth", &fifo->tx_fifo_depth);
 	if (ret) {
 		dev_err(fifo->dt_device, "missing xlnx,tx-fifo-depth property\n");
-		ret = -EIO;
-		goto end;
-	}
-
-	ret = of_property_read_u32(node, "xlnx,use-rx-data",
-				   &fifo->has_rx_fifo);
-	if (ret) {
-		dev_err(fifo->dt_device, "missing xlnx,use-rx-data property\n");
-		ret = -EIO;
-		goto end;
+		return -EINVAL;
 	}
 
-	ret = of_property_read_u32(node, "xlnx,use-tx-data",
-				   &fifo->has_tx_fifo);
-	if (ret) {
-		dev_err(fifo->dt_device, "missing xlnx,use-tx-data property\n");
-		ret = -EIO;
-		goto end;
-	}
+	fifo->has_rx_fifo = of_property_read_bool(node, "xlnx,use-rx-data");
+	fifo->has_tx_fifo = of_property_read_bool(node, "xlnx,use-tx-data");
 
-end:
-	return ret;
+	return 0;
 }
 
 static int axis_fifo_probe(struct platform_device *pdev)
-- 
2.53.0

Re: [PATCH v2 3/3] staging: axis-fifo: fix alignment and handle boolean properties

[Dan Carpenter]

On Fri, Feb 27, 2026 at 03:10:45PM -0300, Lucas Faria Mendes wrote:
> Signed-off-by: Lucas Faria Mendes <lucas.fariamo08@gmail.com>
> ---
>  drivers/staging/axis-fifo/axis-fifo.c | 55 +++++++--------------------
>  1 file changed, 13 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-fifo/axis-fifo.c
> index c64a7249feca..4b2cab2f8357 100644
> --- a/drivers/staging/axis-fifo/axis-fifo.c
> +++ b/drivers/staging/axis-fifo/axis-fifo.c
> @@ -387,66 +387,37 @@ static void axis_fifo_debugfs_init(struct axis_fifo *fifo)
>  
>  static int axis_fifo_parse_dt(struct axis_fifo *fifo)
>  {
> -	int ret;
> -	unsigned int value;
>  	struct device_node *node = fifo->dt_device->of_node;
> -
> -	ret = of_property_read_u32(node, "xlnx,axi-str-rxd-tdata-width",
> -				   &value);
> +	int ret;
> +	
> +	ret = of_property_read_u32(node, "xlnx,axi-str-rxd-tdata-width", &ret);
        ^^^                                                              ^^^^


>  	if (ret) {
>  		dev_err(fifo->dt_device, "missing xlnx,axi-str-rxd-tdata-width property\n");
> -		goto end;
> -	} else if (value != 32) {
> -		dev_err(fifo->dt_device, "xlnx,axi-str-rxd-tdata-width only supports 32 bits\n");
> -		ret = -EIO;
> -		goto end;
> +		return -EINVAL;
>  	}

What?  I'm so puzzled by this patch.  It's totally wrong.

regards,
dan carpenter